Dmitry Stogov
7e782a291a
Extend disassembler to support .rodata section and IP relative data labels
2022-05-26 01:17:02 +03:00
Dmitry Stogov
19e93fd3f6
Allow multi-target test suite
2022-05-25 17:38:22 +03:00
Dmitry Stogov
ac65d71964
ws
2022-05-25 12:02:31 +03:00
Dmitry Stogov
9215162833
Ger rid of ir_ctx.bb_num and double neaning of ir_ctx.prev_insn_len
2022-05-25 11:58:35 +03:00
Dmitry Stogov
740cac8e2f
Move ir_ctx.unused_live_ranges to local variable
2022-05-25 10:57:21 +03:00
Dmitry Stogov
463002107a
Rename "gcm_blocks" into "cfg_map"
2022-05-25 09:33:47 +03:00
Dmitry Stogov
58b67fec18
Topological sort of nodes in each basic block
2022-05-24 18:04:38 +03:00
Dmitry Stogov
04667faf22
Reorder blocks according to branch probability
2022-05-24 12:47:39 +03:00
Dmitry Stogov
d3c1e4a02f
Reorder basic blocks to reduce number of jumps and improve code locality
2022-05-24 00:43:35 +03:00
Dmitry Stogov
d250f77713
Improve type conversion nodes
2022-05-20 09:00:13 +03:00
Dmitry Stogov
c6b0e95d6b
Add type conversion nodes (no code generation yet)
2022-05-20 01:01:48 +03:00
Dmitry Stogov
911219493d
Implement IJMP instruction (indirect jump or computed goto)
2022-05-19 18:56:48 +03:00
Dmitry Stogov
c9bb858e50
Fuse loads without register allocation when this makes sense.
...
Make oarameters passed through stack to reuse the same stack slot for spilling.
2022-05-19 10:53:08 +03:00
Dmitry Stogov
1af065058b
Use better name
2022-05-19 09:15:45 +03:00
Dmitry Stogov
da5de8a390
Introduce IR_PREALLOCATED_STACK flag
2022-05-17 13:15:41 +03:00
Dmitry Stogov
4eaca331b9
Allow using debug_regset in RELEASE build
2022-05-13 09:22:31 +03:00
Dmitry Stogov
1f673ebfda
Better temporary register usage for SSA deconstruction
2022-05-13 00:32:37 +03:00
Dmitry Stogov
386b140265
Refactor Linear Scan Register Allocator to use linked lists instead of bitsets
...
This fixes allocation of several temporary variables for single instruction
2022-05-12 17:43:08 +03:00
Dmitry Stogov
69b5a852e5
Make DESSA API use "ir_ref" instead of "virtual register number"
...
(0 - is still a temporary register)
2022-05-06 16:19:57 +03:00
Dmitry Stogov
9f1ca6b82c
Add IR_LIVE_INTERVAL_TEMP and IR_LIVE_INTERVAL_VAR flags
2022-05-06 09:23:14 +03:00
Dmitry Stogov
dd5a3a3b72
Add flexible support for temporary registers.
...
Get rid of hardcoded temporary registers (incomplete)
2022-05-05 22:35:39 +03:00
Dmitry Stogov
3e6f84eef4
Add "must be in reg" constraint
2022-04-28 14:48:43 +03:00
Dmitry Stogov
2b9e793b4e
Add debug options
2022-04-27 14:47:52 +03:00
Dmitry Stogov
c36efda8a5
Improve register allocation for commutative instructions
...
- swap operands f this make sense
- fix coalescing bug
2022-04-21 16:38:18 +03:00
Dmitry Stogov
bb9813975e
Add IR_OP_FLAG_COMMUTATIVE
2022-04-21 11:30:05 +03:00
Dmitry Stogov
6f3cc3052c
Implement ABS for C code generator
...
Remove POW
2022-04-21 01:00:46 +03:00
Dmitry Stogov
ffdb53821d
Refactor constraint model
...
Each instruction consist from 4 sub positions LOAD, USE, DEF, SAVE.
Hardware constraints are modeled conectiong live intervals and fixed
intervals to different sub-positions.
2022-04-20 18:53:15 +03:00
Dmitry Stogov
705f0f1e1d
VADDR instruction
2022-04-20 12:00:36 +03:00
Dmitry Stogov
51daf5556c
Initial support for ALLOCA, LOAD and STORE (incomplete)
2022-04-19 23:42:05 +03:00
Dmitry Stogov
6b60d8fba9
Code generation for VLOAD and VSTORE
2022-04-19 22:35:29 +03:00
Dmitry Stogov
155c9572c8
Add ability to run "ir_test" with different optimization levels
...
Fix JIT for "cmp mem, imm"
2022-04-19 11:03:01 +03:00
Dmitry Stogov
0922b7cd7f
Add vreg hints
2022-04-15 16:02:23 +03:00
Dmitry Stogov
3f6a6aa3ea
Better CPU constraint model and initial support for live interval splitting (incomplete)
2022-04-14 22:40:13 +03:00
Dmitry Stogov
15b0f10a87
ws
2022-04-11 22:39:52 +03:00
Dmitry Stogov
e2601c8e06
Improve JIT support for IR_CALL
2022-04-07 23:41:38 +03:00
Dmitry Stogov
5b34386f62
Register Allocator suppor for fixed registers, use positions and register hints (incomplete).
2022-04-07 11:11:57 +03:00
Dmitry Stogov
2937993190
Initial import
2022-04-06 00:19:23 +03:00
