Dmitry Stogov
|
09829a9e69
|
Fixed x86_64 calling convention for vararg functions
%al is used as a hidden register to specify the number of passed vector registers
|
2023-09-27 10:23:34 +03:00 |
|
Dmitry Stogov
|
0dbb794399
|
CI tests for MACOS build (#46)
|
2023-08-30 15:24:12 +03:00 |
|
Dmitry Stogov
|
8a5a81c03e
|
Improve live interval splitting and eliminate more redundand spill loads
|
2023-06-27 11:29:26 +03:00 |
|
Dmitry Stogov
|
678a6af863
|
Eliminate duplicate spill loads at the same basic block
|
2023-06-22 14:41:01 +03:00 |
|
Dmitry Stogov
|
85beed7901
|
Fixed incorrect oredering of moves during de-SSA
Temporary de-SSA registers may conflict with outpot registers, therefore these output resisters should be assigned last.
|
2023-06-22 12:07:19 +03:00 |
|
Dmitry Stogov
|
35f94d570f
|
Revert "Eliminate duplicate spill loads at the same basic block"
This reverts commit 5d05d78462.
|
2023-06-22 01:58:26 +03:00 |
|
Dmitry Stogov
|
5d05d78462
|
Eliminate duplicate spill loads at the same basic block
|
2023-06-22 01:24:50 +03:00 |
|
Dmitry Stogov
|
c9d3804b6e
|
Fixed mistakes in GCM algorithm
|
2023-05-29 17:02:50 +03:00 |
|
Dmitry Stogov
|
75edc8fec5
|
Added type compatibility assertion and fixed mistakes in tests
|
2023-05-22 20:48:07 +03:00 |
|
Dmitry Stogov
|
c9fa8dfebd
|
Fixed SSA deconstruction
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
|
2023-05-17 22:37:45 +03:00 |
|
Dmitry Stogov
|
60802d942f
|
Fix previous commit. We still need a temporary register for indirect calls.
|
2023-04-26 14:10:58 +03:00 |
|
Dmitry Stogov
|
9eb366698d
|
Avoid reservaton of temporary resiser for argument passing
We may use any scratch register that is not used for parameters
|
2023-04-26 12:16:05 +03:00 |
|
Dmitry Stogov
|
f85f5fd2a8
|
Remove data dependency between TAILCALL and UNREACHABLE
|
2023-04-13 02:41:28 +03:00 |
|
Dmitry Stogov
|
1e5e9e08ce
|
Re-implement instruction fusion and live-range construction
|
2023-04-05 19:20:43 +03:00 |
|
Dmitry Stogov
|
26e462fa42
|
Add more folding rules
|
2023-03-29 14:07:31 +03:00 |
|
Dmitry Stogov
|
6d36fb12c3
|
Fix example code and test
|
2023-03-23 00:54:47 +03:00 |
|
Dmitry Stogov
|
24e8e216a1
|
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
|
2023-03-23 00:47:27 +03:00 |
|
Dmitry Stogov
|
d26b162ffa
|
Fix register clobbering during argument passing
|
2022-12-26 18:27:53 +03:00 |
|
Dmitry Stogov
|
3e3746d5cb
|
Refactor API that expose target CPU register constraints for register allocator
|
2022-11-17 23:30:35 +03:00 |
|
Dmitry Stogov
|
673779ba6a
|
Use IR_COPY_INT/FP rule instead of IR_COPY op
|
2022-11-16 12:55:40 +03:00 |
|
Dmitry Stogov
|
37dececa71
|
Add more tests (8 tests ara failed on 32-bit x86)
|
2022-11-08 11:56:22 +03:00 |
|