8 Commits

Author	SHA1	Message	Date
Dmitry Stogov	87dbdcea0d	Add necessary compensation loads for bounded nodes when enter into function through OSR entry-point	2023-03-21 13:45:37 +03:00
Dmitry Stogov	5a48805c81	Add support for Windows-64 ABI ("home space") ... Fix parameter passing code to perform sign or zero extension when pass a regiser or a constant TODO: ARM code maight need similar changes	2023-03-02 13:27:01 +03:00
Dmitry Stogov	677c6cb2cb	Move declaration of some register alloation related macros to public API ... Use RLOAD.op3 as a flag to avoid spill store	2023-01-30 16:33:57 +03:00
Dmitry Stogov	3e3746d5cb	Refactor API that expose target CPU register constraints for register allocator	2022-11-17 23:30:35 +03:00
Dmitry Stogov	cc56f12f13	Add LICENSE and copyright notices	2022-11-08 11:32:46 +03:00
Dmitry Stogov	fb998c9058	Aarch64 back-end (incomplete)	2022-06-02 18:34:47 +03:00
Dmitry Stogov	91bddc09ed	Cleanup & unification	2022-06-01 00:34:45 +03:00
Dmitry Stogov	00c300fc9f	Start Aarch64 back-end	2022-05-31 11:22:31 +03:00