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Author SHA1 Message Date
Dmitry Stogov
4cf60c7c5f Validata SSA dominance property 2023-08-31 11:23:24 +03:00
Dmitry Stogov
777566f6f8 An attempt to fix FreeBSD build 2023-08-30 17:44:36 +03:00
Dmitry Stogov
7b534690a4 An attempt to fix FreeBSD build 2023-08-30 17:28:37 +03:00
Dmitry Stogov
4b504aba36 An attempt to fix FreeBSD build 2023-08-30 16:59:30 +03:00
Dmitry Stogov
0dbb794399
CI tests for MACOS build (#46) 2023-08-30 15:24:12 +03:00
Dmitry Stogov
474a8a8d5a Fixed incorrect constant truncation 2023-08-30 12:07:52 +03:00
Dmitry Stogov
c09877b4ef Fix compilation warnings 2023-08-30 09:31:14 +03:00
Dmitry Stogov
a25f85e5dd Fix support for difference in qsort_r/s() on Windows, MAC and GNU 2023-08-30 02:35:06 +03:00
Dmitry Stogov
439f202aed Support for difference in qsort_r() on MAC and GNU 2023-08-30 00:52:24 +03:00
Dmitry Stogov
bacd55fbda Fix compilation warning 2023-08-30 00:28:33 +03:00
Dmitry Stogov
dd2ecad299 Allow reuse of spill slots for objecs of smaller size 2023-08-02 13:20:13 +03:00
Dmitry Stogov
283f1a3a13 Avoid generation of dead PHI 2023-08-01 14:43:57 +03:00
Dmitry Stogov
9df73782ed Fixed support for fake contol edges between END and ENTRY 2023-08-01 13:07:49 +03:00
Dmitry Stogov
1d49fe6cc4 Reduce cost of disabled IR_ASSERT() 2023-07-27 11:16:00 +03:00
Dmitry Stogov
c2a53d29fa Rearrange code for better performance 2023-07-26 22:32:14 +03:00
Dmitry Stogov
0f12ea8c71 Add comments for expanded DynASM macros 2023-07-26 22:05:01 +03:00
Dmitry Stogov
e60bb978f4 Use _xlat[] slots for "used constants" markers 2023-07-07 13:57:01 +03:00
Dmitry Stogov
4bb03ab7e3 ws 2023-07-07 11:53:11 +03:00
Dmitry Stogov
5b90420b18 Improved unused constant elimination 2023-07-07 11:15:52 +03:00
Dmitry Stogov
496a98708e Improved IR linearization 2023-07-07 02:11:03 +03:00
Dmitry Stogov
ef201cd349 Use xlat[] directly (instead of "scheduled" bitset). 2023-07-06 19:34:20 +03:00
Dmitry Stogov
78c377ed2d Store negarive block number in schedule_early() and postive in 
schedule_late(). This eliminates a need for "visited" bitset.
 2023-07-06 19:30:56 +03:00
Dmitry Stogov
d41abefd58 Move processing of the last node of the block out of the loop 2023-07-06 14:10:50 +03:00
Dmitry Stogov
59dbef0cfb typo 2023-07-06 12:59:33 +03:00
Dmitry Stogov
f6cf9140da Update ir_insn.inputs_count and use it after ir_build_def_use_lists() 2023-07-06 01:15:08 +03:00
Dmitry Stogov
d7d7d5fc1b Implemented a faster ir_build_def_use_lists() with higher temporary memory requirement 2023-07-05 16:44:09 +03:00
Dmitry Stogov
8c331e3264 typo 2023-07-04 18:22:15 +03:00
Dmitry Stogov
da9c406cf5 Always build ir_ctx.cfg_map during scheduling (it's used for spill code placement) 2023-07-04 16:37:21 +03:00
Dmitry Stogov
19e08d42e9 Cleanup 2023-07-04 15:19:35 +03:00
Dmitry Stogov
ea7b921f1b Cleanup 2023-07-04 12:19:24 +03:00
Dmitry Stogov
c52fa3e6e0 Clenaup and new folding rules 2023-07-04 12:15:38 +03:00
Dmitry Stogov
444806bd72 Fix Makefile 2023-07-04 10:36:15 +03:00
Dmitry Stogov
cf28a299cd Fix Makefile dependencies 2023-07-04 10:03:33 +03:00
Dmitry Stogov
72a8fcf0f5 typo 2023-07-04 09:23:08 +03:00
Dmitry Stogov
5eb09ce7a5 Add comments 2023-07-04 09:22:28 +03:00
Dmitry Stogov
51d1bbbe09
Merge pull request #45 from weltling/example_func_call 
examples: Add native function call example
 2023-07-03 09:37:56 +03:00
Anatol Belski
c437cc6df6 examples: Add native function call example 
Signed-off-by: Anatol Belski <anbelski@linux.microsoft.com>
 2023-07-02 18:41:43 +02:00
Dmitry Stogov
ce2d6ceba6 Fixed non-boolean constant GUARD condition checks 2023-06-29 23:49:20 +03:00
Dmitry Stogov
7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result 
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
 2023-06-29 12:42:44 +03:00
Dmitry Stogov
865daeb988 Duxed support for multi-word instructions 2023-06-29 00:29:18 +03:00
Dmitry Stogov
2bfe1626ad Change ir_allocate_blocked_reg() according to description from "Optimized Interval Splitting in a Linear Scan Register Allocator" 2023-06-28 22:00:50 +03:00
Dmitry Stogov
b1e6ae66e3 More accurate reslution of a register allocation conflict 2023-06-28 16:17:21 +03:00
Dmitry Stogov
1b88d998c8 Fixed inactive interval splitting 2023-06-27 15:48:35 +03:00
Dmitry Stogov
b9fc218604 Remove first part of splitted inactive interval from the "inactive" list 2023-06-27 15:04:10 +03:00
Dmitry Stogov
141d46f5d8 Fixed tests 2023-06-27 11:34:13 +03:00
Dmitry Stogov
8a5a81c03e Improve live interval splitting and eliminate more redundand spill loads 2023-06-27 11:29:26 +03:00
Dmitry Stogov
9cec28c188 Fixed compilation warnings 2023-06-22 14:50:14 +03:00
Dmitry Stogov
678a6af863 Eliminate duplicate spill loads at the same basic block 2023-06-22 14:41:01 +03:00
Dmitry Stogov
85beed7901 Fixed incorrect oredering of moves during de-SSA 
Temporary de-SSA registers may conflict with outpot registers, therefore these output resisters should be assigned last.
 2023-06-22 12:07:19 +03:00
Dmitry Stogov
35f94d570f Revert "Eliminate duplicate spill loads at the same basic block" 
This reverts commit 5d05d78462.
 2023-06-22 01:58:26 +03:00