67 Commits

Author	SHA1	Message	Date
Dmitry Stogov	4e917faaba	Fix stack parameters loading	2022-05-17 15:00:58 +03:00
Dmitry Stogov	1e7059d7e0	Pass arguments through stack in reverse order	2022-05-17 12:34:31 +03:00
Dmitry Stogov	6fb5380906	Take into account spill slot size and alignment	2022-05-16 22:16:29 +03:00
Dmitry Stogov	8496780ece	Fix temporary register usage for parralel arguments passing	2022-05-16 15:34:36 +03:00
Dmitry Stogov	a3b597feef	Use different interval for registers clobbered by CALL	2022-05-13 15:53:54 +03:00
Dmitry Stogov	1f673ebfda	Better temporary register usage for SSA deconstruction	2022-05-13 00:32:37 +03:00
Dmitry Stogov	69b5a852e5	Make DESSA API use "ir_ref" instead of "virtual register number" ... (0 - is still a temporary register)	2022-05-06 16:19:57 +03:00
Dmitry Stogov	2403fa1edc	Fix spill loads during argument passing	2022-05-06 12:55:07 +03:00
Dmitry Stogov	b580c926e6	Avoid need for temporary register for parameters loading	2022-05-06 11:27:24 +03:00
Dmitry Stogov	89f320d7b7	Add SWITCH support for temporary registers	2022-05-06 10:00:19 +03:00
Dmitry Stogov	dd5a3a3b72	Add flexible support for temporary registers. ... Get rid of hardcoded temporary registers (incomplete)	2022-05-05 22:35:39 +03:00
Dmitry Stogov	310f605d6c	Fix register clobbering	2022-04-26 22:49:41 +03:00
Dmitry Stogov	4a6c8d60a6	Fix ALLOCA to align stack frame	2022-04-22 12:55:38 +03:00
Dmitry Stogov	549ac2efd9	Add test	2022-04-22 11:32:59 +03:00
Dmitry Stogov	c47de38bab	Merge spill slots for VAR, VLOAD and VSTORE (this may be unsafe)	2022-04-22 11:30:33 +03:00
Dmitry Stogov	034ef95e07	Allow memory update instructions (without loading into register)	2022-04-22 01:40:10 +03:00
Dmitry Stogov	84b2bac02c	Add more tests	2022-04-22 00:11:34 +03:00