Dmitry Stogov
a3b597feef
Use different interval for registers clobbered by CALL
2022-05-13 15:53:54 +03:00
Dmitry Stogov
896ddb9e77
Flexable scratch register constraints (allow MUL %edx)
2022-05-13 15:10:15 +03:00
Dmitry Stogov
1f673ebfda
Better temporary register usage for SSA deconstruction
2022-05-13 00:32:37 +03:00
Dmitry Stogov
69b5a852e5
Make DESSA API use "ir_ref" instead of "virtual register number"
...
(0 - is still a temporary register)
2022-05-06 16:19:57 +03:00
Dmitry Stogov
2403fa1edc
Fix spill loads during argument passing
2022-05-06 12:55:07 +03:00
Dmitry Stogov
b580c926e6
Avoid need for temporary register for parameters loading
2022-05-06 11:27:24 +03:00
Dmitry Stogov
89f320d7b7
Add SWITCH support for temporary registers
2022-05-06 10:00:19 +03:00
Dmitry Stogov
dd5a3a3b72
Add flexible support for temporary registers.
...
Get rid of hardcoded temporary registers (incomplete)
2022-05-05 22:35:39 +03:00
Dmitry Stogov
7de4566498
Add tests for 64-bit constants
2022-05-04 15:37:07 +03:00
Dmitry Stogov
310f605d6c
Fix register clobbering
2022-04-26 22:49:41 +03:00
Dmitry Stogov
4a6c8d60a6
Fix ALLOCA to align stack frame
2022-04-22 12:55:38 +03:00
Dmitry Stogov
549ac2efd9
Add test
2022-04-22 11:32:59 +03:00
Dmitry Stogov
c47de38bab
Merge spill slots for VAR, VLOAD and VSTORE (this may be unsafe)
2022-04-22 11:30:33 +03:00
Dmitry Stogov
034ef95e07
Allow memory update instructions (without loading into register)
2022-04-22 01:40:10 +03:00
Dmitry Stogov
84b2bac02c
Add more tests
2022-04-22 00:11:34 +03:00
Dmitry Stogov
6f3cc3052c
Implement ABS for C code generator
...
Remove POW
2022-04-21 01:00:46 +03:00
Dmitry Stogov
506e7b658f
Implement ABS and NEG
2022-04-21 00:31:28 +03:00
Dmitry Stogov
ffdb53821d
Refactor constraint model
...
Each instruction consist from 4 sub positions LOAD, USE, DEF, SAVE.
Hardware constraints are modeled conectiong live intervals and fixed
intervals to different sub-positions.
2022-04-20 18:53:15 +03:00
Dmitry Stogov
e449345514
Fix few CSSP bugs
2022-04-19 16:45:03 +03:00
Dmitry Stogov
0922b7cd7f
Add vreg hints
2022-04-15 16:02:23 +03:00
Dmitry Stogov
f04433999f
Reload loading to avoid register clobbering
2022-04-15 15:22:17 +03:00
Dmitry Stogov
3cb707522f
Allocate scratch (caller-saved) registers first
2022-04-15 14:22:35 +03:00
Dmitry Stogov
2c2f2dabab
Better use placement
2022-04-15 00:35:02 +03:00
Dmitry Stogov
3f6a6aa3ea
Better CPU constraint model and initial support for live interval splitting (incomplete)
2022-04-14 22:40:13 +03:00
Dmitry Stogov
d8e7a8579f
Use LEA for 32-bit integers
2022-04-14 18:11:43 +03:00
Dmitry Stogov
9ccefcf973
Support for more instruction in C backend and BOOL_NOT in x86_86
2022-04-08 19:02:11 +03:00
Dmitry Stogov
f1cc9a4ddb
Added tests for unary integer instructions
2022-04-08 16:40:28 +03:00
Dmitry Stogov
fa7a34c629
Support for unordered floating point comparison
2022-04-08 15:29:05 +03:00
Dmitry Stogov
552aeec7d5
x86_64: Optimize integer comparison with zero
2022-04-08 10:49:22 +03:00
Dmitry Stogov
0f92e7dc67
Added more x86_64 tests for integer comparison
2022-04-08 10:05:42 +03:00
Dmitry Stogov
67b23a95b5
Added x86_64 tests for integer comparison
2022-04-08 00:59:45 +03:00
Dmitry Stogov
14f4fdf29d
Added few more basic x86_64 tests
2022-04-08 00:29:49 +03:00
Dmitry Stogov
baf3d31526
ws
2022-04-07 23:31:03 +03:00
Dmitry Stogov
a28f18a712
Added few basic x86_64 tests
2022-04-07 23:24:29 +03:00
Dmitry Stogov
5b34386f62
Register Allocator suppor for fixed registers, use positions and register hints (incomplete).
2022-04-07 11:11:57 +03:00
Dmitry Stogov
2937993190
Initial import
2022-04-06 00:19:23 +03:00