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95 Commits 2 Branches 0 Tags 3.2 MiB
b3c61507a4
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41 Commits

Author SHA1 Message Date
Dmitry Stogov
b3c61507a4 Fixed possible incorrect splitting 2022-04-29 18:50:57 +03:00
Dmitry Stogov
102b367d64 cleanup 2022-04-29 15:24:41 +03:00
Dmitry Stogov
f5f9614854 cleanup 2022-04-29 14:19:53 +03:00
Dmitry Stogov
23945c4bdc Better debug logging 2022-04-29 12:14:26 +03:00
Dmitry Stogov
2e3ba321f8 Swap UsePos flags and prefer to reload registers that SHOULD be in a CPU register 2022-04-29 03:39:32 +03:00
Dmitry Stogov
3e6f84eef4 Add "must be in reg" constraint 2022-04-28 14:48:43 +03:00
Dmitry Stogov
ea46798aeb Fix live interval splitting and second chance binpacking (it seems to work, but may be icomplete) 2022-04-28 13:09:55 +03:00
Dmitry Stogov
acffada3b1 Fix interval processing order 2022-04-28 10:27:01 +03:00
Dmitry Stogov
fffc0ad2ef Delay spill slot allocation 2022-04-28 10:16:02 +03:00
Dmitry Stogov
53532fcb39 Select better register 2022-04-28 01:25:10 +03:00
Dmitry Stogov
5b7a7decd0 Fix splitting of use positions 2022-04-28 00:12:01 +03:00
Dmitry Stogov
9287830a77 Process remaining splits after all unhandled intervals 2022-04-27 23:31:20 +03:00
Dmitry Stogov
59b63cbb91 Sort oputput UsePos after inputs 2022-04-27 21:24:51 +03:00
Dmitry Stogov
7f8f186abd Fix the way as linera-scan walks through splitted intervals 2022-04-27 18:18:53 +03:00
Dmitry Stogov
6e77f886cb LSRA tweaks 2022-04-27 15:02:51 +03:00
Dmitry Stogov
2b9e793b4e Add debug options 2022-04-27 14:47:52 +03:00
Dmitry Stogov
c89246f35a Replace asserts with checks 2022-04-27 01:34:29 +03:00
Dmitry Stogov
329e1f5a44 Fix splitting (incomplete) 2022-04-27 01:04:03 +03:00
Dmitry Stogov
beaa2744e1 Keep fixed live intervals after coalescing 2022-04-26 21:16:22 +03:00
Dmitry Stogov
1370629b47 Fixed interval sorting 2022-04-26 11:51:48 +03:00
Dmitry Stogov
6548818887 Improve interval splitting (incomplete) 2022-04-26 00:54:07 +03:00
Dmitry Stogov
648d7084bc Fix intrval reconstruction after operand swapping 2022-04-25 21:00:01 +03:00
Dmitry Stogov
034ef95e07 Allow memory update instructions (without loading into register) 2022-04-22 01:40:10 +03:00
Dmitry Stogov
84b2bac02c Add more tests 2022-04-22 00:11:34 +03:00
Dmitry Stogov
c36efda8a5 Improve register allocation for commutative instructions 
- swap operands f this make sense
- fix coalescing bug
 2022-04-21 16:38:18 +03:00
Dmitry Stogov
20c9f2e92a Add comment 2022-04-20 19:30:28 +03:00
Dmitry Stogov
ffdb53821d Refactor constraint model 
Each instruction consist from 4 sub positions LOAD, USE, DEF, SAVE.
Hardware constraints are modeled conectiong live intervals and fixed
intervals to different sub-positions.
 2022-04-20 18:53:15 +03:00
Dmitry Stogov
6b60d8fba9 Code generation for VLOAD and VSTORE 2022-04-19 22:35:29 +03:00
Dmitry Stogov
879c4e75f5 Update vreg hints when compacting 2022-04-15 16:14:42 +03:00
Dmitry Stogov
0922b7cd7f Add vreg hints 2022-04-15 16:02:23 +03:00
Dmitry Stogov
9f24f34aca Cleanup 2022-04-15 14:46:03 +03:00
Dmitry Stogov
3cb707522f Allocate scratch (caller-saved) registers first 2022-04-15 14:22:35 +03:00
Dmitry Stogov
2c2f2dabab Better use placement 2022-04-15 00:35:02 +03:00
Dmitry Stogov
3f6a6aa3ea Better CPU constraint model and initial support for live interval splitting (incomplete) 2022-04-14 22:40:13 +03:00
Dmitry Stogov
58c80c48e0 Create fixed interval for a temporary register used for DESSA moves 2022-04-12 16:09:53 +03:00
Dmitry Stogov
14f4fdf29d Added few more basic x86_64 tests 2022-04-08 00:29:49 +03:00
Dmitry Stogov
e2601c8e06 Improve JIT support for IR_CALL 2022-04-07 23:41:38 +03:00
Dmitry Stogov
02863d7dc9 Initial JIT support for IR_CALL 2022-04-07 18:08:06 +03:00
Dmitry Stogov
23bd7fb272 Add hints and fixed intrvals for parameters 2022-04-07 14:18:59 +03:00
Dmitry Stogov
5b34386f62 Register Allocator suppor for fixed registers, use positions and register hints (incomplete). 2022-04-07 11:11:57 +03:00
Dmitry Stogov
2937993190 Initial import 2022-04-06 00:19:23 +03:00