Dmitry Stogov
24f58e7759
Comment assertion to allow PHP/JIT/Win64 work
...
Win64 calling convention defines volatile FP registers.
PHP JIT for Win64 saves and restores only GP registers.
This potentionaly may cause register clobbering and unexpected behavior.
2023-03-03 16:04:54 +03:00
Dmitry Stogov
1542048331
Fix TAILCALL on WIN64
2023-03-02 22:08:24 +03:00
Dmitry Stogov
09d5ecc607
Fix support for WIN64 calling convention
2023-03-02 17:56:15 +03:00
Dmitry Stogov
5a48805c81
Add support for Windows-64 ABI ("home space")
...
Fix parameter passing code to perform sign or zero extension when pass a regiser or a constant
TODO: ARM code maight need similar changes
2023-03-02 13:27:01 +03:00
Dmitry Stogov
e2810c070e
Save and restore used non-volatile XMM registers in prologue and epilogue.
...
We currently save only "single double" part of the registers using
"movsd" instruction. In general, we should save and restore the whole XMM
registers.
2023-02-28 18:12:29 +03:00
Dmitry Stogov
eb771b1fef
Fix incorrect shift operand
2023-02-28 02:22:09 +03:00
Dmitry Stogov
9b34731d16
Fix most MSVC compilation warnings
2023-02-28 02:11:09 +03:00
Dmitry Stogov
00d5e471ad
Improve load fusion, register allocateion and code selection for ADD
2023-02-21 22:55:47 +03:00
Dmitry Stogov
637fe28e90
Add comments
2023-02-21 15:41:41 +03:00
Arnaud Le Blanc
e95cdd0722
Fix temporary register allocation for IR_STORE_INT
...
ir_get_target_constraints() mistakenly tests the instruction type and value
instead of the operands'.
2023-02-18 13:18:49 +01:00
Dmitry Stogov
2f2fed89bb
Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32")
2023-02-17 18:11:13 +03:00
Dmitry Stogov
c71076d3f0
Allow reservation stack for passing arguments
2023-02-17 15:52:26 +03:00
Dmitry Stogov
fd653528e9
JMP optimization. Lift constant IJMP targets into jmp_table(s).
2023-02-16 22:41:55 +03:00
Dmitry Stogov
ec8489bf6f
Fix spill load
2023-02-16 01:46:16 +03:00
Dmitry Stogov
c7e2cca534
Add hint to reuse register in ZEXT/SEXT
2023-02-15 18:33:02 +03:00
Dmitry Stogov
1d7ab16c2a
Allow load fuson for CALL and TAILCALL with arguments
2023-02-14 14:51:12 +03:00
Dmitry Stogov
e19ecd94c3
Eliminate unnecessary "test" or comparison instruction for IF(CMP_OP(BIN_OP(_, _), 0))
...
TODO: this should be ported to ARM
2023-02-14 11:25:16 +03:00
Dmitry Stogov
6a4187eacc
Fixed CLANG build
2023-02-07 23:11:16 +03:00
Dmitry Stogov
d7ed2fdfad
We can't relay on block order because they are re-scheduled later
2023-02-07 03:30:44 +03:00
Dmitry Stogov
2e31446e37
Better 'jp' elimination for IR_CMP_AND_BRANCH_FP
2023-02-07 01:57:07 +03:00
Dmitry Stogov
6521c0b7e4
Better 'jp' elimination for GUARDs
2023-02-07 01:06:30 +03:00
Dmitry Stogov
1773bb81aa
Make a decision about load fusion and operand swapping together
2023-02-05 14:48:14 +03:00
Dmitry Stogov
cfc959d8ca
Better load fusion
2023-02-03 12:50:00 +03:00
Dmitry Stogov
dc728853a2
JMP optimization for GUARDs (guard failur is unexpected)
...
TODO: this should be ported to ARM
2023-02-01 14:51:36 +03:00
Dmitry Stogov
743696fe03
Simplify condition
2023-01-31 16:15:08 +03:00
Dmitry Stogov
038b1e43cd
We can't preallocate stack for fastcall function calls
2023-01-31 16:13:15 +03:00
Dmitry Stogov
677c6cb2cb
Move declaration of some register alloation related macros to public API
...
Use RLOAD.op3 as a flag to avoid spill store
2023-01-30 16:33:57 +03:00
Dmitry Stogov
4fb50d85aa
Add assertion when allocated preserved register is not saved in "fixed" frame prologue
2023-01-26 12:49:23 +03:00
Dmitry Stogov
771da56d07
Fix incorrect tests for empty basic blocks
2023-01-24 11:48:21 +03:00
Dmitry Stogov
a5c0514b13
Use better conditions
2023-01-23 16:05:06 +03:00
Dmitry Stogov
afc948def6
Fix 32-bit negation
2023-01-20 16:00:23 +03:00
Dmitry Stogov
32ad3d1052
Use inline functions to avoid false positive address sanitaizer warnings
2023-01-20 15:35:02 +03:00
Dmitry Stogov
3ac58893f2
Fix address sanitizer warnings
2023-01-20 11:30:22 +03:00
Dmitry Stogov
5103c18269
Fix load fusion in combination with depended register spill load
2023-01-19 13:39:29 +03:00
Dmitry Stogov
208e0040ae
Prefer 'ADD [addr], %r1' over 'mov [addr], %r1; lea [%r1, %r2], %r3'
2022-12-28 22:24:42 +03:00
Dmitry Stogov
e067ff66f3
Allow fuse load of constant address
2022-12-28 09:10:16 +03:00
Dmitry Stogov
b043955723
First opernad of IMUL3 can not be constant
2022-12-28 09:09:19 +03:00
Dmitry Stogov
54597bc862
Clear destination regeister before INT to FP conversion to avoid partial register stall
2022-12-28 00:05:23 +03:00
Dmitry Stogov
cc8f3fe987
Fix register allocation for intervals started by RLOAD of non-fixed register.
...
These intervals may be split and spilled.
2022-12-27 22:34:52 +03:00
Dmitry Stogov
d528d29872
Fix memory leaks in case of dynasm errors and JIT buffer overflow
2022-12-26 20:58:54 +03:00
Dmitry Stogov
67da9e93ea
Fix register clobbering during argument passing and spill load
2022-12-26 20:25:11 +03:00
Dmitry Stogov
d26b162ffa
Fix register clobbering during argument passing
2022-12-26 18:27:53 +03:00
Dmitry Stogov
1df594fea5
Fix memory leak
2022-12-26 14:17:48 +03:00
Dmitry Stogov
cfa8dac9d9
Fix load fusion
2022-12-21 23:32:16 +03:00
Dmitry Stogov
53ead9d2e7
Generate better code for GUARD(_, AND(_, _), _)
2022-12-16 15:07:18 +03:00
Dmitry Stogov
e884e045de
Avoid zero extension to the same register
2022-12-16 13:38:58 +03:00
Dmitry Stogov
95729f76bf
Use IMUL instead of MUL
2022-12-16 12:57:40 +03:00
Dmitry Stogov
4d7386d342
Fix support for spill loads
2022-12-15 23:27:30 +03:00
Dmitry Stogov
837c59156f
Fix support for load fusion of constant address
2022-12-14 13:22:38 +03:00
Dmitry Stogov
47771c73bc
Fix inaccurate address fusion
2022-12-13 17:40:08 +03:00
Dmitry Stogov
52842a094a
Require temporary register for passing argument through stack
2022-12-12 18:14:31 +03:00
Dmitry Stogov
bfbae48e6f
Fix load fusion with spilling
2022-12-09 15:08:43 +03:00
Dmitry Stogov
6790ebf3b5
Implement AFREE instruction to revert ALLOCA
2022-12-07 13:09:00 +03:00
Dmitry Stogov
374df90797
Fix missing sill store
2022-12-07 00:02:02 +03:00
Dmitry Stogov
83d3480391
Fix incorrect spill load inside a fuse load
2022-12-06 23:37:10 +03:00
Dmitry Stogov
0f9d525157
Fix suport for load fusion with constant address
2022-12-05 20:06:42 +03:00
Dmitry Stogov
9a9c6f2aaf
Prevent fusion into LEA if operands are reused somewere else
2022-12-01 16:24:20 +03:00
Dmitry Stogov
daf659a457
Fix incorrect conditions
2022-12-01 00:43:42 +03:00
Dmitry Stogov
25ab83e5a3
iBetter address fusion for constant addresses
2022-11-30 18:16:04 +03:00
Dmitry Stogov
6a4e239773
Create a sparate pass to remove unreachableble CFG blocks.
...
SCCP pass removes unreachable blocks before CFG construction.
In case of -O0 or -O1 pipeline (without SCCP) it's simpler and faster
to unlink unreachable CFG blocks once, then check for reachability
in almost any compilation pass.
-O2 pipeline (with SCCP) don't need this pass.
2022-11-29 20:02:07 +03:00
Dmitry Stogov
c9212a1f57
Add missed slot for "fixed" live_intervals for all "scratch" registers
2022-11-22 09:26:25 +03:00
Dmitry Stogov
ef6c59ad8f
Avoid instruction selection for the first instructionis of basic blocks
2022-11-18 15:07:19 +03:00
Dmitry Stogov
dde8309108
Use reference to previous instruction instead of its length
2022-11-18 13:59:49 +03:00
Dmitry Stogov
00395f0a23
Cleanup: separate ir_phi_input_number() function
2022-11-18 10:11:16 +03:00
Dmitry Stogov
3e3746d5cb
Refactor API that expose target CPU register constraints for register allocator
2022-11-17 23:30:35 +03:00
Dmitry Stogov
118fec9bf7
Fix SNAPSHOT handling
2022-11-16 15:27:34 +03:00
Dmitry Stogov
7015050f22
Simplify CMP_AND_BRANCH and GUARD_CMP via introducing SKIP_CMP rule
2022-11-16 14:09:04 +03:00
Dmitry Stogov
05127b1b13
Remove duplicate code and allow load fusion of IR_SHIFT.op2
2022-11-16 13:20:58 +03:00
Dmitry Stogov
673779ba6a
Use IR_COPY_INT/FP rule instead of IR_COPY op
2022-11-16 12:55:40 +03:00
Dmitry Stogov
3535fd2fc4
Fix compilation warnings and signed/unsigned mess
2022-11-08 23:09:35 +03:00
Dmitry Stogov
cc73788981
Fix compilation warnings
2022-11-08 18:17:29 +03:00
Dmitry Stogov
cc56f12f13
Add LICENSE and copyright notices
2022-11-08 11:32:46 +03:00
Dmitry Stogov
d619efa0ad
Add support for ENDBR
2022-10-27 12:58:04 +03:00
Dmitry Stogov
3af9e1a062
Move some common code into ir_emit.c
2022-10-26 22:52:19 +03:00
Dmitry Stogov
1b84570aa3
Intoduce ir_emit.c that shuould keep common part for different targets
2022-10-26 22:06:07 +03:00
Dmitry Stogov
9b7835a05e
Use ir_emit_exitgroup() helper API instead of IR_EXITGROUP node
2022-10-26 15:46:59 +03:00
Dmitry Stogov
2dea40bfab
Add API to patch native code
2022-10-26 13:44:44 +03:00
Dmitry Stogov
edd7bc7101
Access ctx->rules[] trough inline function with assertion
...
Fix incorrect accesses
2022-10-26 12:49:34 +03:00
Dmitry Stogov
b99d98979f
Limit CMP+GUARD fusing
2022-10-25 22:09:32 +03:00
Dmitry Stogov
006bee10c7
Add checks for constant references before checking the corresponding rule
2022-10-25 20:36:22 +03:00
Dmitry Stogov
ba90e2825e
SNAPSHOT data shouldn't be in registers
2022-10-25 12:22:49 +03:00
Dmitry Stogov
9f472c1c91
Add support for deoptimization and binding to multiple slots
2022-10-21 17:16:25 +03:00
Dmitry Stogov
6667b7efae
Fix register allocation (one of operands MUST be in a register)
2022-10-21 12:02:31 +03:00
Dmitry Stogov
3d175e1576
Fix fuse load
2022-10-18 13:53:00 +03:00
Dmitry Stogov
81c90972d6
Avoid useless spill stores
2022-10-12 12:09:52 +03:00
Dmitry Stogov
678da7fcc1
Use proper MOV instructions
2022-10-12 12:01:49 +03:00
Dmitry Stogov
db8a80e8d5
Temporary remove "pxor".
...
It should be added before all "cvt*" instructions
2022-09-29 20:05:00 +03:00
Dmitry Stogov
0da4b43de8
Fix second argument address
2022-09-29 14:17:54 +03:00
Dmitry Stogov
33bc4ce956
Fixed comparison with zero
2022-09-29 11:31:07 +03:00
Dmitry Stogov
494c9225a9
Refactor trace related helpers
2022-09-29 01:25:42 +03:00
Dmitry Stogov
fdaa0cea54
Ignore dead TLS loads
2022-09-28 21:56:10 +03:00
Dmitry Stogov
a1361d77ba
Support for calling FASTCALL variable functions.
...
Currutly this done through BITCAST hack.
It may make sense to implement full support for function prototypes.
2022-09-28 20:48:35 +03:00
Dmitry Stogov
924f5949f2
Fixed SSE operands alignment and 32-bit support
2022-09-27 20:36:34 +03:00
Dmitry Stogov
408b8d2e4b
Fixed support for GUARD/GUARD_NOT
2022-09-27 16:52:15 +03:00
Dmitry Stogov
31220b1de9
Add code generators for missing GUARDs
2022-09-26 20:47:29 +03:00
Dmitry Stogov
da11454058
Fix incorrect code for IJMP
2022-09-26 14:45:12 +03:00
Dmitry Stogov
2b4a7d2cb3
Fix out of bounds array access
2022-09-23 12:36:11 +03:00
Dmitry Stogov
8f5768628a
Initial support for tracing JIT
2022-09-23 12:22:59 +03:00
Dmitry Stogov
05fd1f971d
Better LOAD fusion
2022-09-21 23:54:45 +03:00
Dmitry Stogov
12c183f391
Added support for GUARD_OVERFLOW
2022-09-20 17:38:27 +03:00