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351 Commits 2 Branches 0 Tags 3.2 MiB
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63 Commits

Author SHA1 Message Date
Dmitry Stogov
32198c00b7 Reimplement JMP optimization 2022-08-30 23:15:20 +03:00
Dmitry Stogov
36a5bdaf43 Improve support for fixed prologue/epilogue 2022-08-11 13:32:44 +03:00
Dmitry Stogov
1820972a21 Use PHP memory manager 2022-08-10 17:41:14 +03:00
Dmitry Stogov
3c4135576a Add TRAP instruction 2022-07-20 17:59:44 +03:00
Dmitry Stogov
907c22261d Turn IR_TLS into "load" 2022-06-28 00:03:06 +03:00
Dmitry Stogov
fe333adfa1 Add ability to force fix/restore some predefied registers 2022-06-23 22:39:00 +03:00
Dmitry Stogov
1bc5dc43dd Add IR_STUB flag 2022-06-23 17:06:22 +03:00
Dmitry Stogov
c9fa87e6c4 Support for fastcall caling convention. 
(this should be reimplemented through function prototypes)
 2022-06-23 13:14:30 +03:00
Dmitry Stogov
56c8b372a8 Replace ir_insn.emit_const by ir_insn.const_flags 2022-06-23 11:25:47 +03:00
Dmitry Stogov
2148f05392 Initial support for fascall calling convention (incomplete) 2022-06-22 23:59:56 +03:00
Dmitry Stogov
a165c43196 Initial support for thread local storage + optimization of some related code selection patterns 2022-06-22 16:02:43 +03:00
Dmitry Stogov
082bcf89c9 Use ir_ctx.fixed_regset to limit available registers 2022-06-21 16:13:14 +03:00
Dmitry Stogov
be054efb97 Use function API intead of macros 2022-06-21 11:24:42 +03:00
Dmitry Stogov
411dd20331 Support for code fragments with multiple entries 2022-06-16 23:49:27 +03:00
Dmitry Stogov
ac5c3981e5 Allow LOOP_BEGIN to have multiple input back-edges 2022-06-16 12:31:23 +03:00
Dmitry Stogov
3f6c1ee0f5 cleanup 2022-06-15 22:48:19 +03:00
Dmitry Stogov
5fb115ab11 Remove LOOP_EXIT 2022-06-15 17:27:31 +03:00
Dmitry Stogov
f841fb6c34 Initial support for guards 2022-06-14 16:27:33 +03:00
Dmitry Stogov
af4558e439 Allow emitting native code into preallocated buffer 2022-06-10 11:30:19 +03:00
Dmitry Stogov
5cafe50d36 Initial support for PHP 2022-06-10 00:16:29 +03:00
Dmitry Stogov
ad052c59ab cleanup 2022-06-06 22:36:11 +03:00
Dmitry Stogov
30e11861dd Aarch64 back-end (incomplete) 2022-06-03 00:38:49 +03:00
Dmitry Stogov
91bddc09ed Cleanup & unification 2022-06-01 00:34:45 +03:00
Dmitry Stogov
00c300fc9f Start Aarch64 back-end 2022-05-31 11:22:31 +03:00
Dmitry Stogov
41f3e43cf7 cleanup 2022-05-27 13:18:04 +03:00
Dmitry Stogov
3e1816a71f Fix register allocation for ABS_INT 2022-05-27 00:11:31 +03:00
Dmitry Stogov
7e782a291a Extend disassembler to support .rodata section and IP relative data labels 2022-05-26 01:17:02 +03:00
Dmitry Stogov
19e93fd3f6 Allow multi-target test suite 2022-05-25 17:38:22 +03:00
Dmitry Stogov
ac65d71964 ws 2022-05-25 12:02:31 +03:00
Dmitry Stogov
9215162833 Ger rid of ir_ctx.bb_num and double neaning of ir_ctx.prev_insn_len 2022-05-25 11:58:35 +03:00
Dmitry Stogov
740cac8e2f Move ir_ctx.unused_live_ranges to local variable 2022-05-25 10:57:21 +03:00
Dmitry Stogov
463002107a Rename "gcm_blocks" into "cfg_map" 2022-05-25 09:33:47 +03:00
Dmitry Stogov
58b67fec18 Topological sort of nodes in each basic block 2022-05-24 18:04:38 +03:00
Dmitry Stogov
04667faf22 Reorder blocks according to branch probability 2022-05-24 12:47:39 +03:00
Dmitry Stogov
d3c1e4a02f Reorder basic blocks to reduce number of jumps and improve code locality 2022-05-24 00:43:35 +03:00
Dmitry Stogov
d250f77713 Improve type conversion nodes 2022-05-20 09:00:13 +03:00
Dmitry Stogov
c6b0e95d6b Add type conversion nodes (no code generation yet) 2022-05-20 01:01:48 +03:00
Dmitry Stogov
911219493d Implement IJMP instruction (indirect jump or computed goto) 2022-05-19 18:56:48 +03:00
Dmitry Stogov
c9bb858e50 Fuse loads without register allocation when this makes sense. 
Make oarameters passed through stack to reuse the same stack slot for spilling.
 2022-05-19 10:53:08 +03:00
Dmitry Stogov
1af065058b Use better name 2022-05-19 09:15:45 +03:00
Dmitry Stogov
da5de8a390 Introduce IR_PREALLOCATED_STACK flag 2022-05-17 13:15:41 +03:00
Dmitry Stogov
4eaca331b9 Allow using debug_regset in RELEASE build 2022-05-13 09:22:31 +03:00
Dmitry Stogov
1f673ebfda Better temporary register usage for SSA deconstruction 2022-05-13 00:32:37 +03:00
Dmitry Stogov
386b140265 Refactor Linear Scan Register Allocator to use linked lists instead of bitsets 
This fixes allocation of several temporary variables for single instruction
 2022-05-12 17:43:08 +03:00
Dmitry Stogov
69b5a852e5 Make DESSA API use "ir_ref" instead of "virtual register number" 
(0 - is still a temporary register)
 2022-05-06 16:19:57 +03:00
Dmitry Stogov
9f1ca6b82c Add IR_LIVE_INTERVAL_TEMP and IR_LIVE_INTERVAL_VAR flags 2022-05-06 09:23:14 +03:00
Dmitry Stogov
dd5a3a3b72 Add flexible support for temporary registers. 
Get rid of hardcoded temporary registers (incomplete)
 2022-05-05 22:35:39 +03:00
Dmitry Stogov
3e6f84eef4 Add "must be in reg" constraint 2022-04-28 14:48:43 +03:00
Dmitry Stogov
2b9e793b4e Add debug options 2022-04-27 14:47:52 +03:00
Dmitry Stogov
c36efda8a5 Improve register allocation for commutative instructions 
- swap operands f this make sense
- fix coalescing bug
 2022-04-21 16:38:18 +03:00