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479 Commits 2 Branches 0 Tags 3.2 MiB
c8dc4e9e74
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117 Commits

Author SHA1 Message Date
Dmitry Stogov
c8dc4e9e74 Move ir_input_edges_count(phi) out of the loop, because all PHIs inherit their arity from MERGE/LOOP_BEGIN 2022-11-09 21:54:01 +03:00
Dmitry Stogov
3535fd2fc4 Fix compilation warnings and signed/unsigned mess 2022-11-08 23:09:35 +03:00
Dmitry Stogov
cc73788981 Fix compilation warnings 2022-11-08 18:17:29 +03:00
Dmitry Stogov
cc56f12f13 Add LICENSE and copyright notices 2022-11-08 11:32:46 +03:00
Dmitry Stogov
22385c1528 Allocate and reuse spill slots using simple linear-scan (without holes) 2022-11-02 21:53:05 +03:00
Dmitry Stogov
0a5bb4a571 Better condition 2022-11-02 21:28:56 +03:00
Dmitry Stogov
802ec945ad Reorder conditions for the most common case 2022-11-02 16:27:26 +03:00
Dmitry Stogov
3af9e1a062 Move some common code into ir_emit.c 2022-10-26 22:52:19 +03:00
Dmitry Stogov
4b114914dc Prevent register clobbering 2022-10-25 12:24:05 +03:00
Dmitry Stogov
265ebc1000 Fix two LSRA edge cases 2022-10-24 21:55:59 +03:00
Dmitry Stogov
9f472c1c91 Add support for deoptimization and binding to multiple slots 2022-10-21 17:16:25 +03:00
Dmitry Stogov
22cd9265d3 Check if the register is necessary at all 2022-10-18 22:02:09 +03:00
Dmitry Stogov
3ef58e5c2e Take into account RLOADs for non fixed registers 2022-10-11 22:23:09 +03:00
Dmitry Stogov
f5c0151740 Remove hints to the same virtual register 2022-10-05 20:31:20 +03:00
Dmitry Stogov
e9402c8436 Add hint for "op1" if result reuses "op1" register. 
This improves register allocation if regiter for result was coalesced and allocated before the register for operand.
 2022-10-05 17:58:37 +03:00
Dmitry Stogov
45fff1fe5f Implement binding IR node to VAR (assign spill slot) 2022-09-20 11:03:25 +03:00
Dmitry Stogov
9aac7e76af Requre opearnad to be in register 2022-09-15 22:18:35 +03:00
Dmitry Stogov
a0c9405ae7 Fixed memory leak 2022-09-15 20:32:20 +03:00
Dmitry Stogov
e6f6e92d66 Improve spill code fusion 2022-09-15 17:52:28 +03:00
Dmitry Stogov
ad59556d85 Add support for binding IR nodes to "external" spill slots (e.g. PHP VM stack slots) 2022-09-15 15:26:43 +03:00
Dmitry Stogov
d4cd0d6eba Better interval splitting 2022-09-15 01:50:25 +03:00
Dmitry Stogov
cdc34ae22b Prohibit swapping of operands when the first operand is constant 2022-09-14 14:28:57 +03:00
Dmitry Stogov
76028e8855 Fix compilation warnings 2022-09-05 22:43:27 +03:00
Dmitry Stogov
756a1afc82 Better register allocation support for address and load fusion 2022-09-01 19:19:01 +03:00
Dmitry Stogov
b0cba142a9 Merge ir_uses_fixed_reg() into ir_get_def_flags() and ir_get_use_flags() 2022-08-12 21:17:19 +03:00
Dmitry Stogov
b607a28b2a Fix 2022-08-12 21:01:35 +03:00
Dmitry Stogov
360ca107f4 Replace dirst ir_bitset_union() by ir_bitset_copy() 2022-08-12 19:52:24 +03:00
Dmitry Stogov
d55154d998 Introduce ir_bitqueue API 2022-08-12 19:25:10 +03:00
Dmitry Stogov
9ff5d74778 Introduce ir_bitset_pop_first_ex() and ir_bitset_incl_ex() to avoid repatable checks of the first bitset elements. 2022-08-12 18:01:15 +03:00
Dmitry Stogov
253b99ae74 Eliminate useless ir_bitset_empty() checks 2022-08-11 20:42:03 +03:00
Dmitry Stogov
ca109d3fc9 Use single live interval to handle all scratch registers clobbered by CALL 2022-08-11 19:56:59 +03:00
Dmitry Stogov
1820972a21 Use PHP memory manager 2022-08-10 17:41:14 +03:00
Dmitry Stogov
825d18a5cf Reprder conditions 2022-08-10 15:37:14 +03:00
Dmitry Stogov
8ed4a4d2fa Cleanup "current_range" cache maintenance 2022-08-10 15:24:09 +03:00
Dmitry Stogov
8861c6cf54 Construct unhandled list in backward order to simplify the list sorting 2022-08-10 15:04:01 +03:00
Dmitry Stogov
1ef04d2540 Improve live interval coverage and overlaping tests by checking only the necessary tails of active and inactive intervals. 2022-08-10 13:59:34 +03:00
Dmitry Stogov
89013100c8 Optimize ir_ival_covers() (the list of live ranges is sorted) 2022-08-10 10:38:30 +03:00
Dmitry Stogov
0295c071cf Cache the last ir_live_range.end in ir_live_interval.end 2022-08-10 09:47:06 +03:00
Dmitry Stogov
2148f05392 Initial support for fascall calling convention (incomplete) 2022-06-22 23:59:56 +03:00
Dmitry Stogov
082bcf89c9 Use ir_ctx.fixed_regset to limit available registers 2022-06-21 16:13:14 +03:00
Dmitry Stogov
00e92483bc Fix compilation warnings 2022-06-21 11:41:59 +03:00
Dmitry Stogov
5ef1e97261 Better support for unreachable basic blocks 2022-06-20 16:34:44 +03:00
Dmitry Stogov
5cafe50d36 Initial support for PHP 2022-06-10 00:16:29 +03:00
Dmitry Stogov
3212cd5bd2 Fix compilation warnings 2022-06-07 14:43:35 +03:00
Dmitry Stogov
91bddc09ed Cleanup & unification 2022-06-01 00:34:45 +03:00
Dmitry Stogov
00c300fc9f Start Aarch64 back-end 2022-05-31 11:22:31 +03:00
Dmitry Stogov
41f3e43cf7 cleanup 2022-05-27 13:18:04 +03:00
Dmitry Stogov
3e1816a71f Fix register allocation for ABS_INT 2022-05-27 00:11:31 +03:00
Dmitry Stogov
2840227291 Fixed assertion 2022-05-26 21:44:36 +03:00
Dmitry Stogov
4974c301bc Fix code generation for preserved registers and dessa moves 2022-05-26 18:08:39 +03:00