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801 Commits

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Author SHA1 Message Date
Dmitry Stogov
862e25d96c Try allocationg another blocked register in case of unresolvable conflicts 2022-12-22 22:09:04 +03:00
Dmitry Stogov
cfa8dac9d9 Fix load fusion 2022-12-21 23:32:16 +03:00
Dmitry Stogov
1bff08bc10 Update use_lists when modify an instruction 2022-12-21 23:31:11 +03:00
Dmitry Stogov
53ead9d2e7 Generate better code for GUARD(_, AND(_, _), _) 2022-12-16 15:07:18 +03:00
Dmitry Stogov
e884e045de Avoid zero extension to the same register 2022-12-16 13:38:58 +03:00
Dmitry Stogov
95729f76bf Use IMUL instead of MUL 2022-12-16 12:57:40 +03:00
Dmitry Stogov
9e54343a62 Fix iteration through loop pre-headers 2022-12-15 23:28:09 +03:00
Dmitry Stogov
4d7386d342 Fix support for spill loads 2022-12-15 23:27:30 +03:00
Dmitry Stogov
1d01ce3a39 Add constant folding rulues for BITCAST 2022-12-15 23:26:45 +03:00
Dmitry Stogov
7773792716 Add constant folding rulues for ADDR 2022-12-15 22:03:25 +03:00
Dmitry Stogov
837c59156f Fix support for load fusion of constant address 2022-12-14 13:22:38 +03:00
Dmitry Stogov
47771c73bc Fix inaccurate address fusion 2022-12-13 17:40:08 +03:00
Dmitry Stogov
52842a094a Require temporary register for passing argument through stack 2022-12-12 18:14:31 +03:00
Dmitry Stogov
bfbae48e6f Fix load fusion with spilling 2022-12-09 15:08:43 +03:00
Dmitry Stogov
5959f5375b Fix missed register allocation for the rest of splitted inactive interval 2022-12-09 15:07:36 +03:00
Dmitry Stogov
6790ebf3b5 Implement AFREE instruction to revert ALLOCA 2022-12-07 13:09:00 +03:00
Dmitry Stogov
efbc51baaa Fixed codegeneration for TRUNC on aarch64 2022-12-07 11:56:53 +03:00
Dmitry Stogov
374df90797 Fix missing sill store 2022-12-07 00:02:02 +03:00
Dmitry Stogov
83d3480391 Fix incorrect spill load inside a fuse load 2022-12-06 23:37:10 +03:00
Dmitry Stogov
0f9d525157 Fix suport for load fusion with constant address 2022-12-05 20:06:42 +03:00
Dmitry Stogov
9dda4e7553 Add constant folding rulues for ADDR 2022-12-05 16:44:10 +03:00
Dmitry Stogov
9a9c6f2aaf Prevent fusion into LEA if operands are reused somewere else 2022-12-01 16:24:20 +03:00
Dmitry Stogov
daf659a457 Fix incorrect conditions 2022-12-01 00:43:42 +03:00
Dmitry Stogov
25ab83e5a3 iBetter address fusion for constant addresses 2022-11-30 18:16:04 +03:00
Dmitry Stogov
6a4e239773 Create a sparate pass to remove unreachableble CFG blocks. 
SCCP pass removes unreachable blocks before CFG construction.
In case of -O0 or -O1 pipeline (without SCCP) it's simpler and faster
to unlink unreachable CFG blocks once, then check for reachability
in almost any compilation pass.
-O2 pipeline (with SCCP) don't need this pass.
 2022-11-29 20:02:07 +03:00
Dmitry Stogov
3f40e70ac9 Don't delay moving up 2022-11-24 17:05:56 +03:00
Dmitry Stogov
a137adfdf9 Separate ir_build_prev_refs(). It's necessary only for -O0 pipeline. 2022-11-24 12:55:16 +03:00
Dmitry Stogov
7fd1ccf48b Eliminte useless checks 2022-11-24 12:23:05 +03:00
Dmitry Stogov
6f8012756e Reuse ir_ctx.prev_ref if the schedule wasn't changed 2022-11-23 16:30:29 +03:00
Dmitry Stogov
bdb8e6a1da Set ir_ctx.prev_ref[] elements for inner BB traversing 2022-11-23 16:16:08 +03:00
Dmitry Stogov
b94f907907 Create ir_ctx.orev_ref[] array in ir_schedule() 2022-11-23 16:15:05 +03:00
Dmitry Stogov
bce0114bab Traverse instruction backward (it's cheaper) 2022-11-23 15:48:22 +03:00
Dmitry Stogov
c5220fdf8d evisit and improve ir_schedule() 2022-11-23 10:22:37 +03:00
Dmitry Stogov
30a26eee85 Revisit and improve ir_build_def_use_list() 2022-11-23 10:22:07 +03:00
Dmitry Stogov
c6aeb417fa Extend test suite to support XFAIL section 2022-11-22 10:43:29 +03:00
Dmitry Stogov
c9212a1f57 Add missed slot for "fixed" live_intervals for all "scratch" registers 2022-11-22 09:26:25 +03:00
Dmitry Stogov
d858872b90
Merge pull request #3 from iluuu1994/github-actions 
Add GitHub actions
 2022-11-22 09:05:21 +03:00
Ilija Tovilo
9060407ada
Add GitHub actions 2022-11-21 20:42:07 +01:00
Dmitry Stogov
ef6c59ad8f Avoid instruction selection for the first instructionis of basic blocks 2022-11-18 15:07:19 +03:00
Dmitry Stogov
7d07a4ac89 Strength reduction 2022-11-18 14:38:19 +03:00
Dmitry Stogov
dde8309108 Use reference to previous instruction instead of its length 2022-11-18 13:59:49 +03:00
Dmitry Stogov
ae19ad7c79 Eliminate unnecessary loops 2022-11-18 12:47:15 +03:00
Dmitry Stogov
00395f0a23 Cleanup: separate ir_phi_input_number() function 2022-11-18 10:11:16 +03:00
Dmitry Stogov
3e3746d5cb Refactor API that expose target CPU register constraints for register allocator 2022-11-17 23:30:35 +03:00
Dmitry Stogov
baa9f44ca2 RLOAD and VAR don't have inputs 2022-11-16 19:21:52 +03:00
Dmitry Stogov
3471060709 Skip END and LOOP_END 2022-11-16 19:06:09 +03:00
Dmitry Stogov
c0e1216361 Improve ir_assign_virtual_registers() 2022-11-16 18:43:34 +03:00
Dmitry Stogov
ba97919e9e Improve ir_assign_virtual_registers() 2022-11-16 18:09:49 +03:00
Dmitry Stogov
118fec9bf7 Fix SNAPSHOT handling 2022-11-16 15:27:34 +03:00
Dmitry Stogov
7015050f22 Simplify CMP_AND_BRANCH and GUARD_CMP via introducing SKIP_CMP rule 2022-11-16 14:09:04 +03:00