Dmitry Stogov
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ce2d6ceba6
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Fixed non-boolean constant GUARD condition checks
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2023-06-29 23:49:20 +03:00 |
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Dmitry Stogov
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9cec28c188
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Fixed compilation warnings
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2023-06-22 14:50:14 +03:00 |
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Dmitry Stogov
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85beed7901
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Fixed incorrect oredering of moves during de-SSA
Temporary de-SSA registers may conflict with outpot registers, therefore these output resisters should be assigned last.
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2023-06-22 12:07:19 +03:00 |
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Dmitry Stogov
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99bcde9e1e
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Cleanup spill related code
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2023-06-21 23:20:58 +03:00 |
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Dmitry Stogov
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d67c212916
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Separate codegen info output into ir_dump_codegen()
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2023-06-21 22:36:36 +03:00 |
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Dmitry Stogov
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ebaefd376a
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Fix stack frame and assign all spill slots before code genearatin
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2023-06-21 19:04:22 +03:00 |
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Dmitry Stogov
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4124ef5150
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Allow printing IR annotated with register-allocation, spill-code-placement, de-SSA and code-generation information
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2023-06-21 13:28:15 +03:00 |
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Dmitry Stogov
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25656607ba
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Variabls with a register constraint may be loaed/stored directly from/to a spill slot (without an additional register)
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2023-06-21 01:14:31 +03:00 |
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Dmitry Stogov
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b37d4e0443
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Allow usage of CPU stack slots for deoptimization
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2023-06-16 02:14:02 +03:00 |
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Dmitry Stogov
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6a98514bdc
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Move stack size related metricks to ir_ctx
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2023-06-15 19:28:54 +03:00 |
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Dmitry Stogov
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311267714e
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Use macros insted of bit ops
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2023-06-14 20:23:32 +03:00 |
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Dmitry Stogov
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defd58cec3
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Store proper %sp register value
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2023-06-13 18:22:21 +03:00 |
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Dmitry Stogov
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257bdff21a
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Fix compilation warnings
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2023-06-09 10:58:58 +03:00 |
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Dmitry Stogov
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b8be0b9dd9
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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Dmitry Stogov
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ae4daf223e
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Replace assertion with a non-fatal error
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2023-06-07 18:39:51 +03:00 |
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Dmitry Stogov
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3de6c5126a
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Avoid code generation for useless loads and stores
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2023-06-07 14:43:16 +03:00 |
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Dmitry Stogov
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186dc6b0a6
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Fixed GH issue #33: IR program failed to compile with "-O0" "-S" options
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2023-06-05 18:22:12 +03:00 |
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Dmitry Stogov
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4e01e7251e
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Implemented support for veneers on AArch64
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2023-06-02 00:49:32 +03:00 |
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Dmitry Stogov
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87f2fc7f69
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Fixed typo
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2023-05-29 15:52:17 +03:00 |
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Dmitry Stogov
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20b9a7513c
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Fixed missing label
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2023-05-26 09:08:57 +03:00 |
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Dmitry Stogov
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2a80257535
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Support for more C escape sequences
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2023-05-22 19:51:19 +03:00 |
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Dmitry Stogov
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d3640495a2
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Ceanup ir_compute_live_ranges() implementation
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2023-05-19 12:34:54 +03:00 |
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Dmitry Stogov
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5c2023fd7f
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Avoid live range constrction for VARs
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2023-05-18 21:00:57 +03:00 |
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Dmitry Stogov
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477dbf7d76
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Avoid live range constrction for RLOAD with fixed registers
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2023-05-18 13:37:12 +03:00 |
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Dmitry Stogov
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c9fa8dfebd
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Fixed SSA deconstruction
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
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2023-05-17 22:37:45 +03:00 |
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Dmitry Stogov
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1bbee7b9da
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Get rid of ir_live_interval.top
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2023-04-28 09:49:12 +03:00 |
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Dmitry Stogov
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60802d942f
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Fix previous commit. We still need a temporary register for indirect calls.
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2023-04-26 14:10:58 +03:00 |
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Dmitry Stogov
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9eb366698d
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Avoid reservaton of temporary resiser for argument passing
We may use any scratch register that is not used for parameters
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2023-04-26 12:16:05 +03:00 |
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Dmitry Stogov
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0de0c1d0fa
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Improve parallel copy algorithm to support move of single source into multiple destinations
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2023-04-26 10:56:55 +03:00 |
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Dmitry Stogov
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1749168078
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Add ir_insn_len() and ir_insn_inputs_to_len() private helpers
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2023-04-21 13:40:55 +03:00 |
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Dmitry Stogov
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e01c43a967
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Simplify access to nodes with variable inputs count
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2023-04-21 12:40:17 +03:00 |
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Dmitry Stogov
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e5c01495da
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Use arena to allocate live_intervals and nested data structures
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2023-04-13 13:47:16 +03:00 |
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Dmitry Stogov
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04795b9f04
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Fix compilation warnings
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2023-04-12 10:48:30 +03:00 |
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Dmitry Stogov
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1e5e9e08ce
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Re-implement instruction fusion and live-range construction
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2023-04-05 19:20:43 +03:00 |
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Dmitry Stogov
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1058cde808
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Cleanup instruction selector
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2023-03-29 01:21:54 +03:00 |
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Dmitry Stogov
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ba0fa44447
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Add "const" modifiers
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2023-03-28 13:18:12 +03:00 |
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Dmitry Stogov
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72a5649236
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Reorder conditions and avoid reloading
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2023-03-23 23:44:59 +03:00 |
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Dmitry Stogov
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7e687262f7
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Remove always true conditions
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2023-03-23 22:16:05 +03:00 |
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Dmitry Stogov
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87dbdcea0d
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Add necessary compensation loads for bounded nodes when enter into function through OSR entry-point
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2023-03-21 13:45:37 +03:00 |
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Dmitry Stogov
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f5b7065b10
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Refactor the ENTRY nodes
Now all ENTRY nodes have a "fake" input control edge.
Through this edge all of them are dominated by START node.
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2023-03-17 09:02:37 +03:00 |
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Dmitry Stogov
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5052a6ca97
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Fix stack alignment and allow non-saved permanent registers in the "fixed" frames
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2023-03-07 21:38:27 +03:00 |
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Dmitry Stogov
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9b34731d16
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Fix most MSVC compilation warnings
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2023-02-28 02:11:09 +03:00 |
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Dmitry Stogov
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637fe28e90
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Add comments
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2023-02-21 15:41:41 +03:00 |
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Dmitry Stogov
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9f81982d86
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Fix 'mov' to/from 'sp' register
sp is shared with zero register and 'mov' for sp/xzr is encoded differently
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2023-02-21 11:42:05 +03:00 |
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Dmitry Stogov
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c71076d3f0
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Allow reservation stack for passing arguments
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2023-02-17 15:52:26 +03:00 |
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Dmitry Stogov
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fd653528e9
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JMP optimization. Lift constant IJMP targets into jmp_table(s).
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2023-02-16 22:41:55 +03:00 |
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Dmitry Stogov
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038b1e43cd
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We can't preallocate stack for fastcall function calls
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2023-01-31 16:13:15 +03:00 |
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Dmitry Stogov
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677c6cb2cb
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Move declaration of some register alloation related macros to public API
Use RLOAD.op3 as a flag to avoid spill store
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2023-01-30 16:33:57 +03:00 |
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Dmitry Stogov
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bbfcb3e8c8
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Fix register allocation for MUL_OV in a different way
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2023-01-26 13:20:08 +03:00 |
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Dmitry Stogov
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4fb50d85aa
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Add assertion when allocated preserved register is not saved in "fixed" frame prologue
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2023-01-26 12:49:23 +03:00 |
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