ir/tests/debug.aarch64/regset-fib.irt
Dmitry Stogov c9fa8dfebd Fixed SSA deconstruction
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
2023-05-17 22:37:45 +03:00

135 lines
2.5 KiB
Plaintext

--TEST--
Fib
--TARGET--
aarch64
--ARGS--
--debug-regset 0x3ffffffff --save --dump-live-ranges -S --run
--CODE--
{
int32_t zero = 0;
double c_0 = 0;
double c_1 = 1;
double c_10000 = 10000;
uintptr_t f = func(printf);
uintptr_t format = "%g\n";
l_1 = START(l_6);
double lo_1 = COPY(c_0);
double hi_1 = COPY(c_1);
l_2 = END(l_1);
l_3 = LOOP_BEGIN(l_2, l_9);
double lo_2 = PHI(l_3, lo_1, lo_3);
double hi_2 = PHI(l_3, hi_1, hi_3);
bool b = LT(hi_2, c_10000);
l_4 = IF(l_3, b);
l_7 = IF_TRUE(l_4);
double hi_3 = ADD(hi_2, lo_2);
double lo_3 = SUB(hi_3, lo_2);
l_8 = CALL/2(l_7, f, format, lo_3);
# ll = CALL/2(l_7, f, format, lo_3);
# l_8 = CALL/2(ll, f, format, lo_3);
l_9 = LOOP_END(l_8);
l_5 = IF_FALSE(l_4);
l_6 = RETURN(l_5, zero);
}
--EXPECT--
{
uintptr_t c_1 = 0;
bool c_2 = 0;
bool c_3 = 1;
int32_t c_4 = 0;
double c_5 = 0;
double c_6 = 1;
double c_7 = 10000;
uintptr_t c_8 = func(printf);
uintptr_t c_9 = "%g\n";
l_1 = START(l_15);
l_2 = END(l_1);
l_3 = LOOP_BEGIN(l_2, l_13);
double d_4 = PHI(l_3, c_5, d_10);
double d_5 = PHI(l_3, c_6, d_9);
bool d_6 = LT(d_5, c_7);
l_7 = IF(l_3, d_6);
l_8 = IF_TRUE(l_7);
double d_9 = ADD(d_5, d_4);
double d_10 = SUB(d_9, d_4);
l_11 = CALL/2(l_8, c_8, c_9, d_10);
l_13 = LOOP_END(l_11);
l_14 = IF_FALSE(l_7);
l_15 = RETURN(l_14, c_4);
}
{ # LIVE-RANGES (vregs_count=2)
TMP
[%d0]: [2.2-2.3)/1
[%d0]: [7.0-7.2)/6.2
R1 (d_4, d_10) [SPILL=0x0]
[%d0]: [3.0-7.0), DEF(4.2)
: [7.0-8.0)
[%d0]: [8.0-10.1), [10.2-11.0), USE(9.1/2)!, USE(10.1/2)!, DEF(10.2)!, USE(11.0/4, hint=%d0)
: [11.0-14.0), PHI_USE(13.2, phi=d_4/3)
R2 (d_5, d_9) [SPILL=0x8]
[%d1]: [3.0-9.1), [9.2-10.1), DEF(5.2), USE(7.1/6.1)!, USE(9.1/1)!, DEF(9.2)!, USE(10.1/1)!
: [10.1-14.0), PHI_USE(13.2, phi=d_5/3)
[%x0] : [11.0-11.1), [15.0-15.1)
[%d0] : [11.0-11.1)
[%SCRATCH] : [11.1-11.2)
}
test:
stp x29, x30, [sp, #-0x20]!
mov x29, sp
fmov d0, xzr
str d0, [x29, #0x10]
ldr d1, .L3
str d1, [x29, #0x18]
.L1:
ldr d0, .L4
ldr d1, [x29, #0x18]
fcmp d0, d1
b.ls .L2
ldr d1, [x29, #0x18]
ldr d0, [x29, #0x10]
fadd d1, d1, d0
str d1, [x29, #0x18]
ldr d1, [x29, #0x18]
ldr d0, [x29, #0x10]
fsub d0, d1, d0
str d0, [x29, #0x10]
ldr d0, [x29, #0x10]
adr x0, .L5
bl _IO_printf
b .L1
.L2:
mov w0, wzr
ldp x29, x30, [sp], #0x20
ret
.rodata
.db 0x1f, 0x20, 0x03, 0xd5
.L3:
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f
.L4:
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0xc3, 0x40
.L5:
.db 0x25, 0x67, 0x0a, 0x00
1
1
2
3
5
8
13
21
34
55
89
144
233
377
610
987
1597
2584
4181
6765
exit code = 0