ir/tests/x86/ra_004.irt
2022-12-16 12:57:40 +03:00

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--TEST--
004: Register Allocation (DIV + MUL)
--TARGET--
x86
--ARGS--
-S
--CODE--
{
l_1 = START(l_4);
uint32_t x_1 = PARAM(l_1, "x", 1);
uint32_t y_1 = PARAM(l_1, "y", 2);
uint32_t z_1 = PARAM(l_1, "z", 3);
uint32_t x_2 = DIV(x_1, y_1);
uint32_t x_3 = MUL(x_2, z_1);
l_4 = RETURN(l_1, x_3);
}
--EXPECT--
test:
movl 4(%esp), %eax
xorl %edx, %edx
divl 8(%esp)
imull 0xc(%esp), %eax
retl