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180 lines
4.0 KiB
C
180 lines
4.0 KiB
C
/*
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* IR - Lightweight JIT Compilation Framework
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* (Aarch64 CPU specific definitions)
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* Copyright (C) 2022 Zend by Perforce.
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* Authors: Dmitry Stogov <dmitry@php.net>
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*/
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#ifndef IR_AARCH64_H
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#define IR_AARCH64_H
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#define IR_GP_REGS(_) \
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_(X0, x0) \
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_(X1, x1) \
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_(X2, x2) \
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_(X3, x3) \
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_(X4, x4) \
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_(X5, x5) \
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_(X6, x6) \
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_(X7, x7) \
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_(X8, x8) \
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_(X9, x9) \
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_(X10, x10) \
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_(X11, x11) \
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_(X12, x12) \
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_(X13, x13) \
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_(X14, x14) \
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_(X15, x15) \
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_(X16, x16) \
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_(X17, x17) \
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_(X18, x18) \
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_(X19, x19) \
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_(X20, x20) \
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_(X21, x21) \
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_(X22, x22) \
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_(X23, x23) \
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_(X24, x24) \
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_(X25, x25) \
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_(X26, x26) \
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_(X27, x27) \
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_(X28, x28) \
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_(X29, x29) \
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_(X30, x30) \
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_(X31, x31) \
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_(PC, pc) \
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# define IR_FP_REGS(_) \
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_(F0, f0) \
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_(F1, f1) \
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_(F2, f2) \
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_(F3, f3) \
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_(F4, f4) \
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_(F5, f5) \
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_(F6, f6) \
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_(F7, f7) \
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_(F8, f8) \
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_(F9, f9) \
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_(F10, f10) \
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_(F11, f11) \
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_(F12, f12) \
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_(F13, f13) \
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_(F14, f14) \
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_(F15, f15) \
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_(F16, f16) \
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_(F17, f17) \
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_(F18, f18) \
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_(F19, f19) \
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_(F20, f20) \
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_(F21, f21) \
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_(F22, f22) \
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_(F23, f23) \
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_(F24, f24) \
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_(F25, f25) \
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_(F26, f26) \
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_(F27, f27) \
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_(F28, f28) \
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_(F29, f29) \
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_(F30, f30) \
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_(F31, f31) \
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#define IR_GP_REG_ENUM(code, name) \
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IR_REG_ ## code,
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#define IR_FP_REG_ENUM(code, name) \
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IR_REG_ ## code,
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enum _ir_reg {
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_IR_REG_NONE = -1,
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IR_GP_REGS(IR_GP_REG_ENUM)
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IR_FP_REGS(IR_FP_REG_ENUM)
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IR_REG_NUM,
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};
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#define IR_REG_GP_FIRST IR_REG_X0
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#define IR_REG_FP_FIRST IR_REG_F0
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#define IR_REG_GP_LAST (IR_REG_FP_FIRST - 1)
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#define IR_REG_FP_LAST (IR_REG_NUM - 1)
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#define IR_REG_SCRATCH (IR_REG_NUM) /* special name for regset */
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#define IR_REG_ALL (IR_REG_NUM + 1) /* special name for regset */
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#define IR_REGSET_64BIT 1
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#define IR_REG_STACK_POINTER \
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IR_REG_X2
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#define IR_REG_FRAME_POINTER \
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IR_REG_X8
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#define IR_REG_LR IR_REG_X1
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#define IR_REG_ZR IR_REG_X0
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#define IR_REGSET_FIXED \
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( IR_REGSET(IR_REG_ZR) \
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| IR_REGSET(IR_REG_LR) \
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| IR_REGSET(IR_REG_STACK_POINTER) \
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| IR_REGSET(IR_REG_X3) /* platform specific register */ \
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| IR_REGSET(IR_REG_FRAME_POINTER))
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#define IR_REGSET_GP \
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IR_REGSET_DIFFERENCE(IR_REGSET_INTERVAL(IR_REG_GP_FIRST, IR_REG_GP_LAST), IR_REGSET_FIXED)
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#define IR_REGSET_FP \
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IR_REGSET_DIFFERENCE(IR_REGSET_INTERVAL(IR_REG_FP_FIRST, IR_REG_FP_LAST), IR_REGSET_FIXED)
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/* Calling Convention */
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#define IR_REG_INT_RET1 IR_REG_X10
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#define IR_REG_FP_RET1 IR_REG_F10
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#define IR_REG_INT_ARGS 8
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#define IR_REG_FP_ARGS 8
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#define IR_REG_INT_ARG1 IR_REG_X10
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#define IR_REG_INT_ARG2 IR_REG_X11
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#define IR_REG_INT_ARG3 IR_REG_X12
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#define IR_REG_INT_ARG4 IR_REG_X13
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#define IR_REG_INT_ARG5 IR_REG_X14
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#define IR_REG_INT_ARG6 IR_REG_X15
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#define IR_REG_INT_ARG7 IR_REG_X16
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#define IR_REG_INT_ARG8 IR_REG_X17
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#define IR_REG_FP_ARG1 IR_REG_F10
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#define IR_REG_FP_ARG2 IR_REG_F11
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#define IR_REG_FP_ARG3 IR_REG_F12
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#define IR_REG_FP_ARG4 IR_REG_F13
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#define IR_REG_FP_ARG5 IR_REG_F14
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#define IR_REG_FP_ARG6 IR_REG_F15
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#define IR_REG_FP_ARG7 IR_REG_F16
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#define IR_REG_FP_ARG8 IR_REG_F17
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#define IR_MAX_REG_ARGS 16
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#define IR_SHADOW_ARGS 0
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# define IR_REGSET_SCRATCH \
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(IR_REGSET_INTERVAL(IR_REG_X5, IR_REG_X7) \
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| IR_REGSET_INTERVAL(IR_REG_X10, IR_REG_X17) \
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| IR_REGSET_INTERVAL(IR_REG_X28, IR_REG_X31) \
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\
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| IR_REGSET_INTERVAL(IR_REG_F0, IR_REG_F7) \
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| IR_REGSET_INTERVAL(IR_REG_F10, IR_REG_F17) \
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| IR_REGSET_INTERVAL(IR_REG_F28, IR_REG_F31))
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# define IR_REGSET_PRESERVED \
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(IR_REGSET_INTERVAL(IR_REG_X8, IR_REG_X9) \
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| IR_REGSET_INTERVAL(IR_REG_X18, IR_REG_X27) \
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\
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| IR_REGSET_INTERVAL(IR_REG_F8, IR_REG_F9) \
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| IR_REGSET_INTERVAL(IR_REG_F18, IR_REG_F27) \)
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typedef struct _ir_tmp_reg {
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union {
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uint8_t num;
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int8_t reg;
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};
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uint8_t type;
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uint8_t start;
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uint8_t end;
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} ir_tmp_reg;
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struct _ir_target_constraints {
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int8_t def_reg;
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uint8_t tmps_count;
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uint8_t hints_count;
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ir_tmp_reg tmp_regs[3];
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int8_t hints[IR_MAX_REG_ARGS + 3];
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};
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#endif /* IR_AARCH64_H */
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