ir/tests/aarch64/ra_011.irt
2022-11-08 11:56:22 +03:00

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--TEST--
011: Register Allocation (ADD + DIV)
--TARGET--
aarch64
--ARGS--
-S
--CODE--
{
l_1 = START(l_4);
uint32_t x_1 = PARAM(l_1, "x", 1);
uint32_t y_1 = PARAM(l_1, "y", 2);
uint32_t z_1 = PARAM(l_1, "z", 3);
uint32_t x_2 = ADD(x_1, y_1);
uint32_t x_3 = DIV(x_2, z_1);
l_4 = RETURN(l_1, x_3);
}
--EXPECT--
test:
add w0, w1, w0
udiv w0, w0, w2
ret