ir/tests/aarch64/ra_014.irt
2022-11-08 11:56:22 +03:00

22 lines
315 B
Plaintext

--TEST--
014: Register Allocation (SHL + SHL)
--TARGET--
aarch64
--ARGS--
-S
--CODE--
{
l_1 = START(l_4);
uint32_t x = PARAM(l_1, "x", 1);
uint32_t y = PARAM(l_1, "y", 2);
uint32_t ret = SHL(x, y);
uint32_t ret2 = SHL(x, ret);
l_4 = RETURN(l_1, ret2);
}
--EXPECT--
test:
lsl w1, w0, w1
lsl w0, w0, w1
ret