mirror of
https://github.com/danog/ir.git
synced 2024-11-30 04:39:43 +01:00
48 lines
1.3 KiB
Plaintext
48 lines
1.3 KiB
Plaintext
- va_arg nodes
|
|
- BSTART, BEND nodes (to free data allocated by ALLOCA)
|
|
- ENTRY node for multy-entry units
|
|
- guards
|
|
- variable name binding
|
|
|
|
- VLOAD, VSTORE -> SSA
|
|
|
|
? reassociation folding rules
|
|
- folding engine improvement (one rule for few patterns)
|
|
|
|
- irreducable loops detection/support
|
|
|
|
- range inference and PI node
|
|
- SCCP edge cases
|
|
- Folding after SCCP (see combo4.ir)
|
|
|
|
- local scheduling according to data dependencies, register presure and pipeline stalls
|
|
- basic block trace scheduling
|
|
|
|
? instruction selection
|
|
- xor, btsl=INCL, btrl=EXCL, btl=IN, bsr
|
|
- MOVZX to avoid a SHIFT and AND instruction
|
|
- Use CMOVcc to remove branches
|
|
- BURS ???
|
|
|
|
? register allocation
|
|
- hints and low priority registers (prevent allocating registers that are used as hints in the following intersecting intervals)
|
|
- spill slot coalescing
|
|
- optimal spill code placement through resolution
|
|
- splinting (spill only at cold path if possible)
|
|
- separate INT and FP allocation phases (for performance)
|
|
|
|
? code generation
|
|
- COND
|
|
- 32-bit x86 back-end
|
|
- binary code emission without DynAsm ???
|
|
|
|
? disassembler
|
|
- .rodata section and relative data labels
|
|
|
|
- modules (functions, data objecs, import, export, prototypes, forward declarations, memory segments, ref data, expr data)
|
|
- C front-end
|
|
- interpreter
|
|
- alias analyzes
|
|
|
|
- PHP support
|