ir/tests/x86/ra_014.irt
2022-11-08 11:56:22 +03:00

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--TEST--
014: Register Allocation (SHL + SHL)
--TARGET--
x86
--ARGS--
-S
--CODE--
{
l_1 = START(l_4);
uint32_t x = PARAM(l_1, "x", 1);
uint32_t y = PARAM(l_1, "y", 2);
uint32_t ret = SHL(x, y);
uint32_t ret2 = SHL(x, ret);
l_4 = RETURN(l_1, ret2);
}
--EXPECT--
test:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl %eax, %edx
shll %cl, %edx
movl %edx, %ecx
shll %cl, %eax
retl