ir/tests/debug
2023-06-22 14:41:01 +03:00
..
args_001.irt
args_002.irt
call2.irt
call3.irt
call_002.irt
call_003.irt
call_alloca.irt
call_vaddr.irt
call-O0.irt
call.irt
combo_001.irt
combo_002.irt
combo_003.irt
combo_004.irt Fixed mistakes in GCM algorithm 2023-05-29 17:02:50 +03:00
dce_001.irt
dessa_001.irt
dessa_002.irt
dessa_003.irt
fig-O0.irt
fig.irt Fixed incorrect oredering of moves during de-SSA 2023-06-22 12:07:19 +03:00
ijmp_001.irt
lea_001.irt
loop_001.irt
loop_002.irt
memop_001.irt
memop_002.irt
memop_003.irt
memop_004.irt
memop_005.irt
memop_006.irt
memop_007.irt
memop_008.irt
memop_009.irt Fix impossible load fusion 2023-06-20 12:14:52 +03:00
memop_010.irt Fix impossible load fusion 2023-06-20 12:14:52 +03:00
params_001.irt Avoid loading of stack parameter to register if this is not necessary 2023-06-09 00:35:15 +03:00
params_002.irt Better usage of the register hints 2023-06-09 16:26:15 +03:00
params_003.irt
ra_001.irt
ra_002.irt Split assign_regs() loop into two versions (with and without spilling). 2023-06-20 08:34:54 +03:00
ra_003.irt Split assign_regs() loop into two versions (with and without spilling). 2023-06-20 08:34:54 +03:00
regset-fib2.irt Eliminate duplicate spill loads at the same basic block 2023-06-22 14:41:01 +03:00
regset-fib.irt Eliminate duplicate spill loads at the same basic block 2023-06-22 14:41:01 +03:00
regset-fibi.irt
regset-test.irt Eliminate duplicate spill loads at the same basic block 2023-06-22 14:41:01 +03:00
sccp_001.irt
sccp_002.irt
swap_001.irt
swap_002.irt
switch_001.irt
switch_002.irt
switch_003.irt
tailcall_001.irt
tailcall_002.irt
test64.irt
test_mem.irt
test_var-O0.irt
test_var.irt
test-mavx.irt
test-O0.irt
test.irt