mirror of
https://github.com/danog/ir.git
synced 2024-11-27 04:45:38 +01:00
ffdb53821d
Each instruction consist from 4 sub positions LOAD, USE, DEF, SAVE. Hardware constraints are modeled conectiong live intervals and fixed intervals to different sub-positions.
75 lines
1.4 KiB
Plaintext
75 lines
1.4 KiB
Plaintext
--TEST--
|
|
020: Translation out of SSA (Figure 1 from "Translating Out of Static Single Assignment Form" by Sreedhar)
|
|
--ARGS--
|
|
--save --dump-live-ranges --dump-cfg
|
|
--CODE--
|
|
{
|
|
uintptr_t c_1 = 0;
|
|
bool c_2 = 0;
|
|
bool c_3 = 1;
|
|
l_1 = START(l_12);
|
|
int32_t d_2 = PARAM(l_1, "a", 0);
|
|
int32_t d_3 = PARAM(l_1, "b", 1);
|
|
bool d_4 = PARAM(l_1, "cond", 2);
|
|
l_5 = IF(l_1, d_4);
|
|
l_6 = IF_TRUE(l_5);
|
|
l_7 = END(l_6);
|
|
l_8 = IF_FALSE(l_5);
|
|
l_9 = END(l_8);
|
|
l_10 = MERGE(l_7, l_9);
|
|
int32_t d_11 = PHI(l_10, d_3, d_2);
|
|
l_12 = RETURN(l_10, d_11);
|
|
}
|
|
--EXPECT--
|
|
{
|
|
uintptr_t c_1 = 0;
|
|
bool c_2 = 0;
|
|
bool c_3 = 1;
|
|
l_1 = START(l_12);
|
|
int32_t d_2 = PARAM(l_1, "a", 0);
|
|
int32_t d_3 = PARAM(l_1, "b", 1);
|
|
bool d_4 = PARAM(l_1, "cond", 2);
|
|
l_5 = IF(l_1, d_4);
|
|
l_6 = IF_TRUE(l_5);
|
|
l_7 = END(l_6);
|
|
l_8 = IF_FALSE(l_5);
|
|
l_9 = END(l_8);
|
|
l_10 = MERGE(l_7, l_9);
|
|
int32_t d_11 = PHI(l_10, d_3, d_2);
|
|
l_12 = RETURN(l_10, d_11);
|
|
}
|
|
{ # CFG
|
|
BB1:
|
|
start=1
|
|
end=5
|
|
successors(2) [BB2, BB3]
|
|
dom_depth=0
|
|
dom_children [BB2, BB3, BB4]
|
|
BB2:
|
|
start=6
|
|
end=7
|
|
successors(1) [BB4]
|
|
predecessors(1) [BB1]
|
|
dom_parent=BB1
|
|
dom_depth=1
|
|
mov R2 -> R1
|
|
BB3:
|
|
start=8
|
|
end=9
|
|
successors(1) [BB4]
|
|
predecessors(1) [BB1]
|
|
dom_parent=BB1
|
|
dom_depth=1
|
|
BB4:
|
|
start=10
|
|
end=12
|
|
predecessors(2) [BB2, BB3]
|
|
dom_parent=BB1
|
|
dom_depth=1
|
|
}
|
|
{ # LIVE-RANGES (vregs_count=3)
|
|
R1 (d_2, d_11): [2.2-6.0), [8.0-12.1), DEF(2.2), DEF(11.2), USE(12.1/2)
|
|
R2 (d_3): [3.2-8.0), DEF(3.2)
|
|
R3 (d_4): [4.2-5.1), DEF(4.2), USE(5.1/2)
|
|
}
|