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b8acbeb5ee
ir/tests/debug.x86
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Dmitry Stogov c9fa8dfebd Fixed SSA deconstruction 
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
2023-05-17 22:37:45 +03:00
..
args_001.irt Improve x86 code generation for passing address of label to stack 2023-03-29 15:48:41 +03:00
args_002.irt Improve x86 code generation for passing address of label to stack 2023-03-29 15:48:41 +03:00
call2.irt Improve x86 code generation for passing address of label to stack 2023-03-29 15:48:41 +03:00
call3.irt Fix previous commit. We still need a temporary register for indirect calls. 2023-04-26 14:10:58 +03:00
call_002.irt Improve x86 code generation for passing address of label to stack 2023-03-29 15:48:41 +03:00
call_alloca.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
call_vaddr.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
call-O0.irt Improve x86 code generation for passing address of label to stack 2023-03-29 15:48:41 +03:00
call.irt Improve x86 code generation for passing address of label to stack 2023-03-29 15:48:41 +03:00
combo_001.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
combo_002.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
combo_003.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
combo_004.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
dce_001.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
dessa_001.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
dessa_002.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
dessa_003.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
fig-O0.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
fig.irt Fix spilling code for arguments passed theought stack and change RA to 2023-04-06 00:16:49 +03:00
ijmp_001.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
lea_001.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
loop_001.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
loop_002.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
memop_001.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
memop_002.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
memop_003.irt Improve load fusion, register allocateion and code selection for ADD 2023-02-21 22:55:47 +03:00
memop_004.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
memop_005.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
memop_006.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
memop_007.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
memop_008.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
params_001.irt Fix spilling code for arguments passed theought stack and change RA to 2023-04-06 00:16:49 +03:00
params_002.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
params_003.irt Improve x86 code generation for passing address of label to stack 2023-03-29 15:48:41 +03:00
regset-fib2.irt Fixed SSA deconstruction 2023-05-17 22:37:45 +03:00
regset-fib.irt Fixed SSA deconstruction 2023-05-17 22:37:45 +03:00
regset-fibi.irt Fixed SSA deconstruction 2023-05-17 22:37:45 +03:00
regset-test.irt Fixed SSA deconstruction 2023-05-17 22:37:45 +03:00
sccp_001.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
sccp_002.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
swap_001.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
swap_002.irt Improve load fusion, register allocateion and code selection for ADD 2023-02-21 22:55:47 +03:00
switch_001.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
switch_002.irt Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00
tailcall_001.irt Remove data dependency between TAILCALL and UNREACHABLE 2023-04-13 02:41:28 +03:00
tailcall_002.irt Remove data dependency between TAILCALL and UNREACHABLE 2023-04-13 02:41:28 +03:00
test_mem.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
test_var-O0.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
test_var.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
test-mavx.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
test-O0.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00
test.irt Remove a "reference" edge from LOOP_END to LOOP_BEGIN node. 2023-03-23 00:47:27 +03:00