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85beed7901
Temporary de-SSA registers may conflict with outpot registers, therefore these output resisters should be assigned last.
107 lines
2.4 KiB
Plaintext
107 lines
2.4 KiB
Plaintext
--TEST--
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Fig
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--TARGET--
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x86_64
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--ARGS--
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-S
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--CODE--
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{
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uintptr_t c_1 = 0;
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bool c_2 = 0;
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bool c_3 = 1;
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int32_t i_1 = 1;
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int32_t i_4 = 4;
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ll_1 = START(ll_16); # <-
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int32_t a_0 = PARAM(ll_1, "a", 0);
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int32_t b_0 = PARAM(ll_1, "b", 1);
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int32_t c_0 = PARAM(ll_1, "c", 2);
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int32_t d_0 = PARAM(ll_1, "d", 3);
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int32_t l_0 = PARAM(ll_1, "l", 4);
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int32_t m_0 = PARAM(ll_1, "m", 5);
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int32_t s_0 = PARAM(ll_1, "s", 6);
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int32_t t_0 = PARAM(ll_1, "t", 7);
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int32_t cond1 = PARAM(ll_1, "cond1", 8);
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int32_t cond2 = PARAM(ll_1, "cond2", 9);
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ll_2 = END(ll_1);
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ll_3 = LOOP_BEGIN(ll_2, ll_12); # <-
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int32_t a_1 = PHI(ll_3, a_0, a_3);
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int32_t d_1 = PHI(ll_3, d_0, d_3);
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int32_t m_1 = PHI(ll_3, m_0, m_3);
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int32_t s_1 = PHI(ll_3, s_0, s_3);
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int32_t t_1 = PHI(ll_3, t_0, t_3);
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ll_4 = IF(ll_3, cond1);
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ll_5 = IF_TRUE(ll_4);
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int32_t l_1 = MUL(c_0, b_0);
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int32_t m_2 = ADD(l_1, i_4);
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int32_t a_2 = COPY(c_0);
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ll_6 = END(ll_5);
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ll_7 = IF_FALSE(ll_4);
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int32_t d_2 = COPY(c_0);
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int32_t l_2 = MUL(d_2, b_0);
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int32_t s_2 = MUL(a_1, b_0);
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int32_t t_2 = ADD(s_2, i_1);
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ll_8 = END(ll_7);
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ll_9 = MERGE(ll_6, ll_8);
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int32_t a_3 = PHI(ll_9, a_2, a_1);
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int32_t d_3 = PHI(ll_9, d_1, d_2);
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int32_t l_3 = PHI(ll_9, l_1, l_2);
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int32_t m_3 = PHI(ll_9, m_2, m_1);
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int32_t s_3 = PHI(ll_9, s_1, s_2);
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int32_t t_3 = PHI(ll_9, t_1, t_2);
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int32_t x_0 = MUL(a_3, b_0);
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int32_t y_0 = ADD(x_0, i_1);
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ll_10 = IF(ll_9, cond2);
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ll_11 = IF_TRUE(ll_10);
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ll_12 = LOOP_END(ll_11);
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ll_13 = IF_FALSE(ll_10);
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int32_t ret1 = ADD(a_3, b_0);
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int32_t ret2 = ADD(ret1, c_0);
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int32_t ret3 = ADD(ret2, d_3);
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int32_t ret4 = ADD(ret3, l_3);
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int32_t ret5 = ADD(ret4, m_3);
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int32_t ret6 = ADD(ret5, s_3);
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int32_t ret7 = ADD(ret6, t_3);
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int32_t ret8 = ADD(ret7, y_0);
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ll_16 = RETURN(ll_13, ret8);
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}
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--EXPECT--
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test:
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subq $0x10, %rsp
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movq %rbx, 8(%rsp)
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movq %rbp, (%rsp)
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movl 0x18(%rsp), %eax
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movl 0x20(%rsp), %r8d
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movl 0x28(%rsp), %r10d
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movl 0x30(%rsp), %r11d
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movl %edx, %ebx
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imull %esi, %ebx
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leal 4(%rbx), %ebp
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.L1:
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testl %r10d, %r10d
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je .L3
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movl %ebp, %r9d
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movl %edx, %edi
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.L2:
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testl %r11d, %r11d
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jne .L1
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movl %edi, %r10d
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imull %esi, %r10d
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addl %edi, %esi
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addl %esi, %edx
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addl %edx, %ecx
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addl %ebx, %ecx
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addl %r9d, %ecx
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addl %ecx, %eax
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addl %r8d, %eax
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leal 1(%rax, %r10), %eax
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movq 8(%rsp), %rbx
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movq (%rsp), %rbp
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addq $0x10, %rsp
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retq
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.L3:
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movl %edi, %eax
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imull %esi, %eax
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leal 1(%rax), %r8d
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movl %edx, %ecx
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jmp .L2
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