ir/tests/debug
2022-04-22 11:30:33 +03:00
..
call2.irt Add more tests 2022-04-22 00:11:34 +03:00
call_vaddr.irt Add more tests 2022-04-22 00:11:34 +03:00
call-O0.irt Add more tests 2022-04-22 00:11:34 +03:00
call.irt Add more tests 2022-04-22 00:11:34 +03:00
combo_001.irt Add more tests 2022-04-22 00:11:34 +03:00
combo_002.irt Add more tests 2022-04-22 00:11:34 +03:00
combo_003.irt Add more tests 2022-04-22 00:11:34 +03:00
combo_004.irt Add more tests 2022-04-22 00:11:34 +03:00
dce_001.irt Add more tests 2022-04-22 00:11:34 +03:00
dessa_001.irt Add more tests 2022-04-22 00:11:34 +03:00
dessa_002.irt Add more tests 2022-04-22 00:11:34 +03:00
dessa_003.irt Add more tests 2022-04-22 00:11:34 +03:00
fig-O0.irt Add more tests 2022-04-22 00:11:34 +03:00
fig.irt Add more tests 2022-04-22 00:11:34 +03:00
lea_001.irt Add more tests 2022-04-22 00:11:34 +03:00
loop_001.irt Add more tests 2022-04-22 00:11:34 +03:00
loop_002.irt Add more tests 2022-04-22 00:11:34 +03:00
memop.irt Allow memory update instructions (without loading into register) 2022-04-22 01:40:10 +03:00
sccp_001.irt Add more tests 2022-04-22 00:11:34 +03:00
sccp_002.irt Add more tests 2022-04-22 00:11:34 +03:00
swap.irt Allow memory update instructions (without loading into register) 2022-04-22 01:40:10 +03:00
switch_001.irt Add more tests 2022-04-22 00:11:34 +03:00
switch_002.irt Add more tests 2022-04-22 00:11:34 +03:00
switch_003.irt Add more tests 2022-04-22 00:11:34 +03:00
tailcall_001.irt Add more tests 2022-04-22 00:11:34 +03:00
test64.irt Add more tests 2022-04-22 00:11:34 +03:00
test_mem.irt Add more tests 2022-04-22 00:11:34 +03:00
test_var.irt Merge spill slots for VAR, VLOAD and VSTORE (this may be unsafe) 2022-04-22 11:30:33 +03:00
test-mavx.irt Add more tests 2022-04-22 00:11:34 +03:00
test-O0.irt Add more tests 2022-04-22 00:11:34 +03:00
test.irt Add more tests 2022-04-22 00:11:34 +03:00