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2022-05-12 21:58:58 +03:00
dynasm Initial import 2022-04-06 00:19:23 +03:00
tests Make DESSA API use "ir_ref" instead of "virtual register number" 2022-05-06 16:19:57 +03:00
.gitignore Added few basic x86_64 tests 2022-04-07 23:24:29 +03:00
gen_ir_fold_hash.c Initial import 2022-04-06 00:19:23 +03:00
ir_cfg.c Initial import 2022-04-06 00:19:23 +03:00
ir_check.c Initial import 2022-04-06 00:19:23 +03:00
ir_disasm.c Added few more basic x86_64 tests 2022-04-08 00:29:49 +03:00
ir_dump.c Fix possible crash 2022-05-11 18:18:28 +03:00
ir_elf.h Initial import 2022-04-06 00:19:23 +03:00
ir_emit_c.c Make DESSA API use "ir_ref" instead of "virtual register number" 2022-05-06 16:19:57 +03:00
ir_fold.h Implement ABS for C code generator 2022-04-21 01:00:46 +03:00
ir_gcm.c Add debug options 2022-04-27 14:47:52 +03:00
ir_gdb.c Initial import 2022-04-06 00:19:23 +03:00
ir_main.c Add debug options 2022-04-27 14:47:52 +03:00
ir_perf.c Initial import 2022-04-06 00:19:23 +03:00
ir_private.h Implement ABS for C code generator 2022-04-21 01:00:46 +03:00
ir_ra.c Refactor Linear Scan Register Allocator to use linked lists instead of bitsets 2022-05-12 17:43:08 +03:00
ir_save.c Code generation for VLOAD and VSTORE 2022-04-19 22:35:29 +03:00
ir_sccp.c Add debug options 2022-04-27 14:47:52 +03:00
ir_strtab.c Initial import 2022-04-06 00:19:23 +03:00
ir_test.c Add debug options 2022-04-27 14:47:52 +03:00
ir_x86.dasc Allow spill slot fusing when swap operands of fp comparison 2022-05-12 21:58:58 +03:00
ir_x86.h Add flexible support for temporary registers. 2022-05-05 22:35:39 +03:00
ir-test.php Added more x86_64 tests for integer comparison 2022-04-08 10:05:42 +03:00
ir.c Add flexible support for temporary registers. 2022-05-05 22:35:39 +03:00
ir.g VADDR instruction 2022-04-20 12:00:36 +03:00
ir.h Refactor Linear Scan Register Allocator to use linked lists instead of bitsets 2022-05-12 17:43:08 +03:00
Makefile Remove temporary test files 2022-05-06 19:19:04 +03:00
test.ir Initial import 2022-04-06 00:19:23 +03:00
TODO Add flexible support for temporary registers. 2022-05-05 22:35:39 +03:00