mirror of
https://github.com/danog/ir.git
synced 2024-11-30 04:39:43 +01:00
1168 lines
30 KiB
C
1168 lines
30 KiB
C
/*
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* IR - Lightweight JIT Compilation Framework
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* (Common data structures and non public definitions)
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* Copyright (C) 2022 Zend by Perforce.
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* Authors: Dmitry Stogov <dmitry@php.net>
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*/
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#ifndef IR_PRIVATE_H
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#define IR_PRIVATE_H
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#include <string.h>
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#include <stdlib.h>
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#ifdef IR_DEBUG
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# include <assert.h>
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# define IR_ASSERT(x) assert(x)
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#else
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# define IR_ASSERT(x)
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#endif
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#ifdef _WIN32
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# include <intrin.h>
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# ifdef _M_X64
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# pragma intrinsic(_BitScanForward64)
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# pragma intrinsic(_BitScanReverse64)
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# endif
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# pragma intrinsic(_BitScanForward)
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# pragma intrinsic(_BitScanReverse)
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#endif
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#ifdef __has_builtin
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# if __has_builtin(__builtin_expect)
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# define EXPECTED(condition) __builtin_expect(!!(condition), 1)
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# define UNEXPECTED(condition) __builtin_expect(!!(condition), 0)
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# endif
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# if __has_attribute(__aligned__)
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# define IR_SET_ALIGNED(alignment, decl) decl __attribute__ ((__aligned__ (alignment)))
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# endif
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# if __has_attribute(__fallthrough__)
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# define IR_FALLTHROUGH __attribute__((__fallthrough__))
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# endif
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#elif defined(_WIN32)
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# define IR_SET_ALIGNED(alignment, decl) __declspec(align(alignment)) decl
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#else /* GCC prior to 10 or non-clang/msvc compilers */
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#define __has_builtin(x) 0
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#endif
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#ifndef EXPECTED
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# define EXPECTED(condition) (condition)
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# define UNEXPECTED(condition) (condition)
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#endif
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#ifndef IR_SET_ALIGNED
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# define IR_SET_ALIGNED(alignment, decl) decl
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#endif
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#ifndef IR_FALLTHROUGH
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# define IR_FALLTHROUGH ((void)0)
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#endif
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/*** Helper routines ***/
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#define IR_ALIGNED_SIZE(size, alignment) \
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(((size) + ((alignment) - 1)) & ~((alignment) - 1))
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#define IR_MAX(a, b) (((a) > (b)) ? (a) : (b))
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#define IR_MIN(a, b) (((a) < (b)) ? (a) : (b))
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#define IR_IS_POWER_OF_TWO(x) (!((x) & ((x) - 1)))
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#define IR_LOG2(x) ir_ntzl(x)
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IR_ALWAYS_INLINE uint8_t ir_rol8(uint8_t op1, uint8_t op2)
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{
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return (op1 << op2) | (op1 >> (8 - op2));
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}
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IR_ALWAYS_INLINE uint16_t ir_rol16(uint16_t op1, uint16_t op2)
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{
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return (op1 << op2) | (op1 >> (16 - op2));
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}
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IR_ALWAYS_INLINE uint32_t ir_rol32(uint32_t op1, uint32_t op2)
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{
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return (op1 << op2) | (op1 >> (32 - op2));
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}
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IR_ALWAYS_INLINE uint64_t ir_rol64(uint64_t op1, uint64_t op2)
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{
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return (op1 << op2) | (op1 >> (64 - op2));
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}
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IR_ALWAYS_INLINE uint8_t ir_ror8(uint8_t op1, uint8_t op2)
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{
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return (op1 >> op2) | (op1 << (8 - op2));
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}
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IR_ALWAYS_INLINE uint16_t ir_ror16(uint16_t op1, uint16_t op2)
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{
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return (op1 >> op2) | (op1 << (16 - op2));
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}
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IR_ALWAYS_INLINE uint32_t ir_ror32(uint32_t op1, uint32_t op2)
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{
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return (op1 >> op2) | (op1 << (32 - op2));
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}
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IR_ALWAYS_INLINE uint64_t ir_ror64(uint64_t op1, uint64_t op2)
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{
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return (op1 >> op2) | (op1 << (64 - op2));
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}
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/* Number of trailing zero bits (0x01 -> 0; 0x40 -> 6; 0x00 -> LEN) */
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IR_ALWAYS_INLINE uint32_t ir_ntz(uint32_t num)
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{
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#if (defined(__GNUC__) || __has_builtin(__builtin_ctz))
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return __builtin_ctz(num);
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#elif defined(_WIN32)
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uint32_t index;
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if (!_BitScanForward(&index, num)) {
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/* undefined behavior */
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return 32;
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}
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return index;
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#else
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int n;
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if (num == 0) return 32;
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n = 1;
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if ((num & 0x0000ffff) == 0) {n += 16; num = num >> 16;}
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if ((num & 0x000000ff) == 0) {n += 8; num = num >> 8;}
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if ((num & 0x0000000f) == 0) {n += 4; num = num >> 4;}
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if ((num & 0x00000003) == 0) {n += 2; num = num >> 2;}
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return n - (num & 1);
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#endif
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}
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/* Number of trailing zero bits (0x01 -> 0; 0x40 -> 6; 0x00 -> LEN) */
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IR_ALWAYS_INLINE uint32_t ir_ntzl(uint64_t num)
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{
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#if (defined(__GNUC__) || __has_builtin(__builtin_ctzl))
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return __builtin_ctzl(num);
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#elif defined(_WIN64)
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unsigned long index;
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if (!_BitScanForward64(&index, num)) {
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/* undefined behavior */
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return 64;
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}
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return (uint32_t) index;
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#else
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uint32_t n;
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if (num == 0) return 64;
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n = 1;
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if ((num & 0xffffffff) == 0) {n += 32; num = num >> 32;}
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if ((num & 0x0000ffff) == 0) {n += 16; num = num >> 16;}
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if ((num & 0x000000ff) == 0) {n += 8; num = num >> 8;}
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if ((num & 0x0000000f) == 0) {n += 4; num = num >> 4;}
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if ((num & 0x00000003) == 0) {n += 2; num = num >> 2;}
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return n - (uint32_t)(num & 1);
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#endif
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}
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/* Number of leading zero bits (Undefined for zero) */
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IR_ALWAYS_INLINE int ir_nlz(uint32_t num)
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{
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#if (defined(__GNUC__) || __has_builtin(__builtin_clz))
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return __builtin_clz(num);
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#elif defined(_WIN32)
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uint32_t index;
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if (!_BitScanReverse(&index, num)) {
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/* undefined behavior */
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return 32;
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}
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return (int) (32 - 1) - index;
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#else
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uint32_t x;
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uint32_t n;
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n = 32;
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x = num >> 16; if (x != 0) {n -= 16; num = x;}
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x = num >> 8; if (x != 0) {n -= 8; num = x;}
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x = num >> 4; if (x != 0) {n -= 4; num = x;}
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x = num >> 2; if (x != 0) {n -= 2; num = x;}
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x = num >> 1; if (x != 0) return n - 2;
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return n - num;
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#endif
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}
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IR_ALWAYS_INLINE int ir_nlzl(uint64_t num)
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{
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#if (defined(__GNUC__) || __has_builtin(__builtin_clzll))
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return __builtin_clzll(num);
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#elif defined(_WIN64)
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unsigned long index;
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if (!_BitScanReverse64(&index, num)) {
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/* undefined behavior */
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return 64;
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}
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return (int) (64 - 1) - index;
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#else
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uint64_t x;
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uint32_t n;
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n = 64;
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x = num >> 32; if (x != 0) {n -= 32; num = x;}
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x = num >> 16; if (x != 0) {n -= 16; num = x;}
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x = num >> 8; if (x != 0) {n -= 8; num = x;}
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x = num >> 4; if (x != 0) {n -= 4; num = x;}
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x = num >> 2; if (x != 0) {n -= 2; num = x;}
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x = num >> 1; if (x != 0) return n - 2;
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return n - (uint32_t)num;
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#endif
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}
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/*** Helper data types ***/
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/* Arena */
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struct _ir_arena {
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char *ptr;
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char *end;
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ir_arena *prev;
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};
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IR_ALWAYS_INLINE ir_arena* ir_arena_create(size_t size)
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{
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ir_arena *arena;
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IR_ASSERT(size >= IR_ALIGNED_SIZE(sizeof(ir_arena), 8));
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arena = (ir_arena*)ir_mem_malloc(size);
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arena->ptr = (char*) arena + IR_ALIGNED_SIZE(sizeof(ir_arena), 8);
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arena->end = (char*) arena + size;
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arena->prev = NULL;
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return arena;
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}
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IR_ALWAYS_INLINE void ir_arena_free(ir_arena *arena)
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{
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do {
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ir_arena *prev = arena->prev;
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ir_mem_free(arena);
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arena = prev;
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} while (arena);
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}
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IR_ALWAYS_INLINE void* ir_arena_alloc(ir_arena **arena_ptr, size_t size)
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{
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ir_arena *arena = *arena_ptr;
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char *ptr = arena->ptr;
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size = IR_ALIGNED_SIZE(size, 8);
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if (EXPECTED(size <= (size_t)(arena->end - ptr))) {
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arena->ptr = ptr + size;
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} else {
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size_t arena_size =
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UNEXPECTED((size + IR_ALIGNED_SIZE(sizeof(ir_arena), 8)) > (size_t)(arena->end - (char*) arena)) ?
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(size + IR_ALIGNED_SIZE(sizeof(ir_arena), 8)) :
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(size_t)(arena->end - (char*) arena);
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ir_arena *new_arena = (ir_arena*)ir_mem_malloc(arena_size);
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ptr = (char*) new_arena + IR_ALIGNED_SIZE(sizeof(ir_arena), 8);
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new_arena->ptr = (char*) new_arena + IR_ALIGNED_SIZE(sizeof(ir_arena), 8) + size;
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new_arena->end = (char*) new_arena + arena_size;
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new_arena->prev = arena;
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*arena_ptr = new_arena;
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}
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return (void*) ptr;
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}
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IR_ALWAYS_INLINE void* ir_arena_checkpoint(ir_arena *arena)
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{
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return arena->ptr;
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}
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IR_ALWAYS_INLINE void ir_release(ir_arena **arena_ptr, void *checkpoint)
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{
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ir_arena *arena = *arena_ptr;
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while (UNEXPECTED((char*)checkpoint > arena->end) ||
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UNEXPECTED((char*)checkpoint <= (char*)arena)) {
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ir_arena *prev = arena->prev;
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ir_mem_free(arena);
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*arena_ptr = arena = prev;
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}
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IR_ASSERT((char*)checkpoint > (char*)arena && (char*)checkpoint <= arena->end);
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arena->ptr = (char*)checkpoint;
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}
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/* Bitsets */
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#if defined(IR_TARGET_X86)
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# define IR_BITSET_BITS 32
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# define IR_BITSET_ONE 1U
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# define ir_bitset_base_t uint32_t
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# define ir_bitset_ntz ir_ntz
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#else
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# define IR_BITSET_BITS 64
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# ifdef _M_X64 /* MSVC*/
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# define IR_BITSET_ONE 1ui64
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# else
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# define IR_BITSET_ONE 1UL
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# endif
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# define ir_bitset_base_t uint64_t
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# define ir_bitset_ntz ir_ntzl
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#endif
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typedef ir_bitset_base_t *ir_bitset;
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IR_ALWAYS_INLINE uint32_t ir_bitset_len(uint32_t n)
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{
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return (n + (IR_BITSET_BITS - 1)) / IR_BITSET_BITS;
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}
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IR_ALWAYS_INLINE ir_bitset ir_bitset_malloc(uint32_t n)
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{
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return ir_mem_calloc(ir_bitset_len(n), IR_BITSET_BITS / 8);
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}
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IR_ALWAYS_INLINE void ir_bitset_incl(ir_bitset set, uint32_t n)
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{
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set[n / IR_BITSET_BITS] |= IR_BITSET_ONE << (n % IR_BITSET_BITS);
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}
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IR_ALWAYS_INLINE void ir_bitset_excl(ir_bitset set, uint32_t n)
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{
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set[n / IR_BITSET_BITS] &= ~(IR_BITSET_ONE << (n % IR_BITSET_BITS));
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}
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IR_ALWAYS_INLINE bool ir_bitset_in(const ir_bitset set, uint32_t n)
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{
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return (set[(n / IR_BITSET_BITS)] & (IR_BITSET_ONE << (n % IR_BITSET_BITS))) != 0;
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}
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IR_ALWAYS_INLINE void ir_bitset_clear(ir_bitset set, uint32_t len)
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{
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memset(set, 0, len * (IR_BITSET_BITS / 8));
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}
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IR_ALWAYS_INLINE void ir_bitset_fill(ir_bitset set, uint32_t len)
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{
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memset(set, 0xff, len * (IR_BITSET_BITS / 8));
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}
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IR_ALWAYS_INLINE bool ir_bitset_empty(const ir_bitset set, uint32_t len)
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{
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uint32_t i;
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for (i = 0; i < len; i++) {
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if (set[i]) {
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return 0;
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}
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}
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return 1;
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}
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IR_ALWAYS_INLINE bool ir_bitset_equal(const ir_bitset set1, const ir_bitset set2, uint32_t len)
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{
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return memcmp(set1, set2, len * (IR_BITSET_BITS / 8)) == 0;
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}
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IR_ALWAYS_INLINE void ir_bitset_copy(ir_bitset set1, const ir_bitset set2, uint32_t len)
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{
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memcpy(set1, set2, len * (IR_BITSET_BITS / 8));
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}
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IR_ALWAYS_INLINE void ir_bitset_intersection(ir_bitset set1, const ir_bitset set2, uint32_t len)
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{
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uint32_t i;
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for (i = 0; i < len; i++) {
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set1[i] &= set2[i];
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}
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}
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IR_ALWAYS_INLINE void ir_bitset_union(ir_bitset set1, const ir_bitset set2, uint32_t len)
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{
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uint32_t i;
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for (i = 0; i < len; i++) {
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set1[i] |= set2[i];
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}
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}
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IR_ALWAYS_INLINE void ir_bitset_difference(ir_bitset set1, const ir_bitset set2, uint32_t len)
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{
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uint32_t i;
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for (i = 0; i < len; i++) {
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set1[i] = set1[i] & ~set2[i];
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}
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}
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IR_ALWAYS_INLINE bool ir_bitset_is_subset(const ir_bitset set1, const ir_bitset set2, uint32_t len)
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{
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uint32_t i;
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for (i = 0; i < len; i++) {
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if (set1[i] & ~set2[i]) {
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return 0;
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}
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}
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return 1;
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}
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IR_ALWAYS_INLINE int ir_bitset_first(const ir_bitset set, uint32_t len)
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{
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uint32_t i;
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for (i = 0; i < len; i++) {
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if (set[i]) {
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return IR_BITSET_BITS * i + ir_bitset_ntz(set[i]);
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}
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}
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return -1; /* empty set */
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}
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IR_ALWAYS_INLINE int ir_bitset_last(const ir_bitset set, uint32_t len)
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{
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uint32_t i = len;
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while (i > 0) {
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i--;
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if (set[i]) {
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uint32_t j = IR_BITSET_BITS * i - 1;
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ir_bitset_base_t x = set[i];
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do {
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x = x >> 1;
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j++;
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} while (x != 0);
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return j;
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}
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}
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return -1; /* empty set */
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}
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IR_ALWAYS_INLINE int ir_bitset_pop_first(ir_bitset set, uint32_t len)
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{
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uint32_t i;
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for (i = 0; i < len; i++) {
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ir_bitset_base_t x = set[i];
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if (x) {
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int bit = IR_BITSET_BITS * i + ir_bitset_ntz(x);
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set[i] = x & (x - 1);
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return bit;
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}
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}
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return -1; /* empty set */
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}
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#define IR_BITSET_FOREACH(set, len, bit) do { \
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ir_bitset _set = (set); \
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uint32_t _i, _len = (len); \
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for (_i = 0; _i < _len; _set++, _i++) { \
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ir_bitset_base_t _x = *_set; \
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while (_x) { \
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(bit) = IR_BITSET_BITS * _i + ir_bitset_ntz(_x); \
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_x &= _x - 1;
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#define IR_BITSET_FOREACH_DIFFERENCE(set1, set2, len, bit) do { \
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ir_bitset _set1 = (set1); \
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ir_bitset _set2 = (set2); \
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uint32_t _i, _len = (len); \
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for (_i = 0; _i < _len; _i++) { \
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ir_bitset_base_t _x = _set1[_i] & ~_set2[_i]; \
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while (_x) { \
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(bit) = IR_BITSET_BITS * _i + ir_bitset_ntz(_x); \
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_x &= _x - 1;
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#define IR_BITSET_FOREACH_END() \
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} \
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} \
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} while (0)
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/* Bit Queue */
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typedef struct _ir_bitqueue {
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uint32_t len;
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uint32_t pos;
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ir_bitset set;
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} ir_bitqueue;
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IR_ALWAYS_INLINE void ir_bitqueue_init(ir_bitqueue *q, uint32_t n)
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{
|
|
q->len = ir_bitset_len(n);
|
|
q->pos = q->len - 1;
|
|
q->set = ir_bitset_malloc(n);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_bitqueue_free(ir_bitqueue *q)
|
|
{
|
|
ir_mem_free(q->set);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_bitqueue_clear(ir_bitqueue *q)
|
|
{
|
|
q->pos = q->len - 1;
|
|
ir_bitset_clear(q->set, q->len);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE int ir_bitqueue_pop(ir_bitqueue *q)
|
|
{
|
|
uint32_t i = q->pos;
|
|
ir_bitset_base_t x, *p = q->set + i;
|
|
do {
|
|
x = *p;
|
|
if (x) {
|
|
int bit = IR_BITSET_BITS * i + ir_bitset_ntz(x);
|
|
*p = x & (x - 1);
|
|
q->pos = i;
|
|
return bit;
|
|
}
|
|
p++;
|
|
i++;
|
|
} while (i < q->len);
|
|
q->pos = q->len - 1;
|
|
return -1; /* empty set */
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_bitqueue_add(ir_bitqueue *q, uint32_t n)
|
|
{
|
|
uint32_t i = n / IR_BITSET_BITS;
|
|
q->set[i] |= IR_BITSET_ONE << (n % IR_BITSET_BITS);
|
|
if (i < q->pos) {
|
|
q->pos = i;
|
|
}
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_bitqueue_del(ir_bitqueue *q, uint32_t n)
|
|
{
|
|
ir_bitset_excl(q->set, n);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE bool ir_bitqueue_in(const ir_bitqueue *q, uint32_t n)
|
|
{
|
|
return ir_bitset_in(q->set, n);
|
|
}
|
|
|
|
/* Dynamic array of numeric references */
|
|
typedef struct _ir_array {
|
|
ir_ref *refs;
|
|
uint32_t size;
|
|
} ir_array;
|
|
|
|
void ir_array_grow(ir_array *a, uint32_t size);
|
|
void ir_array_insert(ir_array *a, uint32_t i, ir_ref val);
|
|
void ir_array_remove(ir_array *a, uint32_t i);
|
|
|
|
IR_ALWAYS_INLINE void ir_array_init(ir_array *a, uint32_t size)
|
|
{
|
|
a->refs = ir_mem_malloc(size * sizeof(ir_ref));
|
|
a->size = size;
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_array_free(ir_array *a)
|
|
{
|
|
ir_mem_free(a->refs);
|
|
a->refs = NULL;
|
|
a->size = 0;
|
|
}
|
|
|
|
IR_ALWAYS_INLINE uint32_t ir_array_size(const ir_array *a)
|
|
{
|
|
return a->size;
|
|
}
|
|
|
|
IR_ALWAYS_INLINE ir_ref ir_array_get(const ir_array *a, uint32_t i)
|
|
{
|
|
return (i < a->size) ? a->refs[i] : IR_UNUSED;
|
|
}
|
|
|
|
IR_ALWAYS_INLINE ir_ref ir_array_at(const ir_array *a, uint32_t i)
|
|
{
|
|
IR_ASSERT(i < a->size);
|
|
return a->refs[i];
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_array_set(ir_array *a, uint32_t i, ir_ref val)
|
|
{
|
|
if (i >= a->size) {
|
|
ir_array_grow(a, i + 1);
|
|
}
|
|
a->refs[i] = val;
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_array_set_unchecked(ir_array *a, uint32_t i, ir_ref val)
|
|
{
|
|
IR_ASSERT(i < a->size);
|
|
a->refs[i] = val;
|
|
}
|
|
|
|
/* List/Stack of numeric references */
|
|
typedef struct _ir_list {
|
|
ir_array a;
|
|
uint32_t len;
|
|
} ir_list;
|
|
|
|
bool ir_list_contains(const ir_list *l, ir_ref val);
|
|
void ir_list_insert(ir_list *l, uint32_t i, ir_ref val);
|
|
void ir_list_remove(ir_list *l, uint32_t i);
|
|
|
|
IR_ALWAYS_INLINE void ir_list_init(ir_list *l, uint32_t size)
|
|
{
|
|
ir_array_init(&l->a, size);
|
|
l->len = 0;
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_list_free(ir_list *l)
|
|
{
|
|
ir_array_free(&l->a);
|
|
l->len = 0;
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_list_clear(ir_list *l)
|
|
{
|
|
l->len = 0;
|
|
}
|
|
|
|
IR_ALWAYS_INLINE uint32_t ir_list_len(const ir_list *l)
|
|
{
|
|
return l->len;
|
|
}
|
|
|
|
IR_ALWAYS_INLINE uint32_t ir_list_capasity(const ir_list *l)
|
|
{
|
|
return ir_array_size(&l->a);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_list_push(ir_list *l, ir_ref val)
|
|
{
|
|
ir_array_set(&l->a, l->len++, val);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_list_push_unchecked(ir_list *l, ir_ref val)
|
|
{
|
|
ir_array_set_unchecked(&l->a, l->len++, val);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE ir_ref ir_list_pop(ir_list *l)
|
|
{
|
|
IR_ASSERT(l->len > 0);
|
|
return ir_array_at(&l->a, --l->len);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE ir_ref ir_list_peek(const ir_list *l)
|
|
{
|
|
IR_ASSERT(l->len > 0);
|
|
return ir_array_at(&l->a, l->len - 1);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE ir_ref ir_list_at(const ir_list *l, uint32_t i)
|
|
{
|
|
IR_ASSERT(i < l->len);
|
|
return ir_array_at(&l->a, i);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_list_set(ir_list *l, uint32_t i, ir_ref val)
|
|
{
|
|
IR_ASSERT(i < l->len);
|
|
ir_array_set_unchecked(&l->a, i, val);
|
|
}
|
|
|
|
/* Worklist (unique list) */
|
|
typedef struct _ir_worklist {
|
|
ir_list l;
|
|
ir_bitset visited;
|
|
} ir_worklist;
|
|
|
|
IR_ALWAYS_INLINE void ir_worklist_init(ir_worklist *w, uint32_t size)
|
|
{
|
|
ir_list_init(&w->l, size);
|
|
w->visited = ir_bitset_malloc(size);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_worklist_free(ir_worklist *w)
|
|
{
|
|
ir_list_free(&w->l);
|
|
ir_mem_free(w->visited);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE uint32_t ir_worklist_len(const ir_worklist *w)
|
|
{
|
|
return ir_list_len(&w->l);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE uint32_t ir_worklist_capasity(const ir_worklist *w)
|
|
{
|
|
return ir_list_capasity(&w->l);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE void ir_worklist_clear(ir_worklist *w)
|
|
{
|
|
ir_list_clear(&w->l);
|
|
ir_bitset_clear(w->visited, ir_bitset_len(ir_worklist_capasity(w)));
|
|
}
|
|
|
|
IR_ALWAYS_INLINE bool ir_worklist_push(ir_worklist *w, ir_ref val)
|
|
{
|
|
IR_ASSERT(val >= 0 && (uint32_t)val < ir_worklist_capasity(w));
|
|
if (ir_bitset_in(w->visited, val)) {
|
|
return 0;
|
|
}
|
|
ir_bitset_incl(w->visited, val);
|
|
IR_ASSERT(ir_list_len(&w->l) < ir_list_capasity(&w->l));
|
|
ir_list_push_unchecked(&w->l, val);
|
|
return 1;
|
|
}
|
|
|
|
IR_ALWAYS_INLINE ir_ref ir_worklist_pop(ir_worklist *w)
|
|
{
|
|
return ir_list_pop(&w->l);
|
|
}
|
|
|
|
IR_ALWAYS_INLINE ir_ref ir_worklist_peek(const ir_worklist *w)
|
|
{
|
|
return ir_list_peek(&w->l);
|
|
}
|
|
|
|
/* IR Hash Table */
|
|
#define IR_INVALID_IDX 0xffffffff
|
|
#define IR_INVALID_VAL 0x80000000
|
|
|
|
typedef struct _ir_hashtab_bucket {
|
|
uint32_t key;
|
|
ir_ref val;
|
|
uint32_t next;
|
|
} ir_hashtab_bucket;
|
|
|
|
typedef struct _ir_hashtab {
|
|
void *data;
|
|
uint32_t mask;
|
|
uint32_t size;
|
|
uint32_t count;
|
|
uint32_t pos;
|
|
} ir_hashtab;
|
|
|
|
void ir_hashtab_init(ir_hashtab *tab, uint32_t size);
|
|
void ir_hashtab_free(ir_hashtab *tab);
|
|
ir_ref ir_hashtab_find(const ir_hashtab *tab, uint32_t key);
|
|
bool ir_hashtab_add(ir_hashtab *tab, uint32_t key, ir_ref val);
|
|
void ir_hashtab_key_sort(ir_hashtab *tab);
|
|
|
|
/*** IR OP info ***/
|
|
extern const uint8_t ir_type_flags[IR_LAST_TYPE];
|
|
extern const char *ir_type_name[IR_LAST_TYPE];
|
|
extern const char *ir_type_cname[IR_LAST_TYPE];
|
|
extern const uint8_t ir_type_size[IR_LAST_TYPE];
|
|
extern const uint32_t ir_op_flags[IR_LAST_OP];
|
|
extern const char *ir_op_name[IR_LAST_OP];
|
|
|
|
#define IR_IS_CONST_OP(op) ((op) > IR_NOP && (op) <= IR_C_FLOAT)
|
|
#define IR_IS_FOLDABLE_OP(op) ((op) <= IR_LAST_FOLDABLE_OP)
|
|
|
|
IR_ALWAYS_INLINE bool ir_const_is_true(const ir_insn *v)
|
|
{
|
|
|
|
if (v->type == IR_BOOL) {
|
|
return v->val.b;
|
|
} else if (IR_IS_TYPE_INT(v->type)) {
|
|
return v->val.i64 != 0;
|
|
} else if (v->type == IR_DOUBLE) {
|
|
return v->val.d != 0.0;
|
|
} else if (v->type == IR_FLOAT) {
|
|
return v->val.f != 0.0;
|
|
}
|
|
IR_ASSERT(0 && "NYI");
|
|
return 0;
|
|
}
|
|
|
|
/* IR OP flags */
|
|
#define IR_OP_FLAG_OPERANDS_SHIFT 3
|
|
|
|
#define IR_OP_FLAG_EDGES_MSK 0x07
|
|
#define IR_OP_FLAG_OPERANDS_MSK 0x38
|
|
#define IR_OP_FLAG_MEM_MASK ((1<<6)|(1<<7))
|
|
|
|
#define IR_OP_FLAG_DATA (1<<8)
|
|
#define IR_OP_FLAG_CONTROL (1<<9)
|
|
#define IR_OP_FLAG_MEM (1<<10)
|
|
#define IR_OP_FLAG_COMMUTATIVE (1<<11)
|
|
#define IR_OP_FLAG_BB_START (1<<12)
|
|
#define IR_OP_FLAG_BB_END (1<<13)
|
|
#define IR_OP_FLAG_TERMINATOR (1<<14)
|
|
|
|
#define IR_OP_FLAG_MEM_LOAD ((0<<6)|(0<<7))
|
|
#define IR_OP_FLAG_MEM_STORE ((0<<6)|(1<<7))
|
|
#define IR_OP_FLAG_MEM_CALL ((1<<6)|(0<<7))
|
|
#define IR_OP_FLAG_MEM_ALLOC ((1<<6)|(1<<7))
|
|
#define IR_OP_FLAG_MEM_MASK ((1<<6)|(1<<7))
|
|
|
|
#define IR_OPND_UNUSED 0x0
|
|
#define IR_OPND_DATA 0x1
|
|
#define IR_OPND_CONTROL 0x2
|
|
#define IR_OPND_CONTROL_DEP 0x3
|
|
#define IR_OPND_CONTROL_REF 0x4
|
|
#define IR_OPND_VAR 0x5
|
|
#define IR_OPND_STR 0x6
|
|
#define IR_OPND_NUM 0x7
|
|
#define IR_OPND_PROB 0x8
|
|
|
|
#define IR_OP_FLAGS(op_flags, op1_flags, op2_flags, op3_flags) \
|
|
((op_flags) | ((op1_flags) << 20) | ((op2_flags) << 24) | ((op3_flags) << 28))
|
|
|
|
#define IR_INPUT_EDGES_COUNT(flags) (flags & IR_OP_FLAG_EDGES_MSK)
|
|
#define IR_OPERANDS_COUNT(flags) ((flags & IR_OP_FLAG_OPERANDS_MSK) >> IR_OP_FLAG_OPERANDS_SHIFT)
|
|
|
|
#define IR_VARIABLE_INPUTS_COUNT 4
|
|
#define IR_PHI_INPUTS_COUNT 5
|
|
|
|
#define IR_IS_FIXED_INPUTS_COUNT(n) ((n) < IR_VARIABLE_INPUTS_COUNT)
|
|
|
|
#define IR_OPND_KIND(flags, i) \
|
|
(((flags) >> (16 + (4 * (((i) > 3) ? 3 : (i))))) & 0xf)
|
|
|
|
#define IR_IS_REF_OPND_KIND(kind) \
|
|
((kind) >= IR_OPND_DATA && (kind) <= IR_OPND_VAR)
|
|
|
|
IR_ALWAYS_INLINE ir_ref ir_variable_inputs_count(const ir_insn *insn)
|
|
{
|
|
uint32_t n = insn->inputs_count;
|
|
if (n == 0) {
|
|
n = 2;
|
|
}
|
|
return n;
|
|
}
|
|
|
|
IR_ALWAYS_INLINE ir_ref ir_operands_count(const ir_ctx *ctx, const ir_insn *insn)
|
|
{
|
|
uint32_t flags = ir_op_flags[insn->op];
|
|
uint32_t n = IR_OPERANDS_COUNT(flags);
|
|
if (EXPECTED(IR_IS_FIXED_INPUTS_COUNT(n))) {
|
|
/* pass */
|
|
} else if (n == IR_VARIABLE_INPUTS_COUNT) {
|
|
/* MERGE or CALL */
|
|
n = ir_variable_inputs_count(insn);
|
|
} else {
|
|
IR_ASSERT(n == IR_PHI_INPUTS_COUNT);
|
|
/* PHI */
|
|
n = ir_variable_inputs_count(&ctx->ir_base[insn->op1]) + 1;
|
|
}
|
|
return n;
|
|
}
|
|
|
|
IR_ALWAYS_INLINE ir_ref ir_input_edges_count(const ir_ctx *ctx, const ir_insn *insn)
|
|
{
|
|
uint32_t flags = ir_op_flags[insn->op];
|
|
uint32_t n = IR_INPUT_EDGES_COUNT(flags);
|
|
if (EXPECTED(IR_IS_FIXED_INPUTS_COUNT(n))) {
|
|
/* pass */
|
|
} else if (n == IR_VARIABLE_INPUTS_COUNT) {
|
|
/* MERGE or CALL */
|
|
n = ir_variable_inputs_count(insn);
|
|
} else {
|
|
IR_ASSERT(n == IR_PHI_INPUTS_COUNT);
|
|
/* PHI */
|
|
n = ir_variable_inputs_count(&ctx->ir_base[insn->op1]) + 1;
|
|
}
|
|
return n;
|
|
}
|
|
|
|
/*** IR Binding ***/
|
|
IR_ALWAYS_INLINE ir_ref ir_binding_find(const ir_ctx *ctx, ir_ref ref)
|
|
{
|
|
ir_ref var = ir_hashtab_find(ctx->binding, ref);
|
|
return (var != (ir_ref)IR_INVALID_VAL) ? var : 0;
|
|
}
|
|
|
|
/*** IR Use Lists ***/
|
|
struct _ir_use_list {
|
|
ir_ref refs; /* index in ir_ctx->use_edges[] array */
|
|
ir_ref count;
|
|
};
|
|
|
|
/*** IR Basic Blocks info ***/
|
|
#define IR_IS_BB_START(op) \
|
|
((ir_op_flags[op] & IR_OP_FLAG_BB_START) != 0)
|
|
|
|
#define IR_IS_BB_MERGE(op) \
|
|
((op) == IR_MERGE || (op) == IR_LOOP_BEGIN)
|
|
|
|
#define IR_IS_BB_END(op) \
|
|
((ir_op_flags[op] & IR_OP_FLAG_BB_END) != 0)
|
|
|
|
#define IR_BB_UNREACHABLE (1<<0)
|
|
#define IR_BB_START (1<<1)
|
|
#define IR_BB_ENTRY (1<<2)
|
|
#define IR_BB_LOOP_HEADER (1<<3)
|
|
#define IR_BB_IRREDUCIBLE_LOOP (1<<4)
|
|
#define IR_BB_DESSA_MOVES (1<<5) /* translation out of SSA requires MOVEs */
|
|
#define IR_BB_EMPTY (1<<6)
|
|
#define IR_BB_PREV_EMPTY_ENTRY (1<<7)
|
|
#define IR_BB_OSR_ENTRY_LOADS (1<<8) /* OSR Entry-point with register LOADs */
|
|
#define IR_BB_LOOP_WITH_ENTRY (1<<9) /* set together with LOOP_HEADER if there is an ENTRY in the loop */
|
|
|
|
struct _ir_block {
|
|
uint32_t flags;
|
|
ir_ref start; /* index of first instruction */
|
|
ir_ref end; /* index of last instruction */
|
|
uint32_t successors; /* index in ir_ctx->cfg_edges[] array */
|
|
uint32_t successors_count;
|
|
uint32_t predecessors; /* index in ir_ctx->cfg_edges[] array */
|
|
uint32_t predecessors_count;
|
|
union {
|
|
uint32_t dom_parent; /* immediate dominator block */
|
|
uint32_t idom; /* immediate dominator block */
|
|
};
|
|
union {
|
|
uint32_t dom_depth; /* depth from the root of the dominators tree */
|
|
uint32_t postnum; /* used temporary during tree constructon */
|
|
};
|
|
uint32_t dom_child; /* first dominated blocks */
|
|
uint32_t dom_next_child; /* next dominated block (linked list) */
|
|
uint32_t loop_header;
|
|
uint32_t loop_depth;
|
|
};
|
|
|
|
uint32_t ir_skip_empty_target_blocks(const ir_ctx *ctx, uint32_t b);
|
|
uint32_t ir_skip_empty_next_blocks(const ir_ctx *ctx, uint32_t b);
|
|
void ir_get_true_false_blocks(const ir_ctx *ctx, uint32_t b, uint32_t *true_block, uint32_t *false_block, uint32_t *next_block);
|
|
|
|
IR_ALWAYS_INLINE uint32_t ir_phi_input_number(const ir_ctx *ctx, const ir_block *bb, uint32_t from)
|
|
{
|
|
uint32_t n, *p;
|
|
|
|
for (n = 0, p = &ctx->cfg_edges[bb->predecessors]; n < bb->predecessors_count; p++, n++) {
|
|
if (*p == from) {
|
|
return n + 2; /* first input is a reference to MERGE */
|
|
}
|
|
}
|
|
IR_ASSERT(0);
|
|
return 0;
|
|
}
|
|
|
|
/*** Folding Engine (see ir.c and ir_fold.h) ***/
|
|
typedef enum _ir_fold_action {
|
|
IR_FOLD_DO_RESTART,
|
|
IR_FOLD_DO_CSE,
|
|
IR_FOLD_DO_EMIT,
|
|
IR_FOLD_DO_COPY,
|
|
IR_FOLD_DO_CONST
|
|
} ir_fold_action;
|
|
|
|
ir_ref ir_folding(ir_ctx *ctx, uint32_t opt, ir_ref op1, ir_ref op2, ir_ref op3, ir_insn *op1_insn, ir_insn *op2_insn, ir_insn *op3_insn);
|
|
|
|
/*** IR Live Info ***/
|
|
typedef ir_ref ir_live_pos;
|
|
typedef struct _ir_use_pos ir_use_pos;
|
|
|
|
#define IR_SUB_REFS_COUNT 4
|
|
|
|
#define IR_LOAD_SUB_REF 0
|
|
#define IR_USE_SUB_REF 1
|
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#define IR_DEF_SUB_REF 2
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#define IR_SAVE_SUB_REF 3
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#define IR_LIVE_POS_TO_REF(pos) ((pos) / IR_SUB_REFS_COUNT)
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#define IR_LIVE_POS_TO_SUB_REF(pos) ((pos) % IR_SUB_REFS_COUNT)
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#define IR_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT)
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#define IR_START_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT)
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#define IR_LOAD_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT + IR_LOAD_SUB_REF)
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#define IR_USE_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT + IR_USE_SUB_REF)
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#define IR_DEF_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT + IR_DEF_SUB_REF)
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#define IR_SAVE_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT + IR_SAVE_SUB_REF)
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#define IR_END_LIVE_POS_FROM_REF(ref) ((ref) * IR_SUB_REFS_COUNT + IR_SUB_REFS_COUNT)
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/* ir_use_pos.flags bits */
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#define IR_USE_MUST_BE_IN_REG (1<<0)
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#define IR_USE_SHOULD_BE_IN_REG (1<<1)
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#define IR_DEF_REUSES_OP1_REG (1<<2)
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#define IR_DEF_CONFLICTS_WITH_INPUT_REGS (1<<3)
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#define IR_FUSED_USE (1<<6)
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#define IR_PHI_USE (1<<7)
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#define IR_OP1_MUST_BE_IN_REG (1<<8)
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#define IR_OP1_SHOULD_BE_IN_REG (1<<9)
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#define IR_OP2_MUST_BE_IN_REG (1<<10)
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#define IR_OP2_SHOULD_BE_IN_REG (1<<11)
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#define IR_OP3_MUST_BE_IN_REG (1<<12)
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#define IR_OP3_SHOULD_BE_IN_REG (1<<13)
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#define IR_USE_FLAGS(def_flags, op_num) (((def_flags) >> (6 + (IR_MIN((op_num), 3) * 2))) & 3)
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struct _ir_use_pos {
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uint16_t op_num; /* 0 - means result */
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int8_t hint;
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uint8_t flags;
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ir_ref hint_ref; /* negative references are used for FUSION anf PHI */
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ir_live_pos pos;
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ir_use_pos *next;
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};
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struct _ir_live_range {
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ir_live_pos start; /* inclusive */
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ir_live_pos end; /* exclusive */
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ir_live_range *next;
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};
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/* ir_live_interval.flags bits (two low bits are reserved for temporary register number) */
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#define IR_LIVE_INTERVAL_FIXED (1<<0)
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#define IR_LIVE_INTERVAL_TEMP (1<<1)
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#define IR_LIVE_INTERVAL_VAR (1<<2)
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#define IR_LIVE_INTERVAL_COALESCED (1<<3)
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#define IR_LIVE_INTERVAL_HAS_HINTS (1<<4)
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#define IR_LIVE_INTERVAL_MEM_PARAM (1<<5)
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#define IR_LIVE_INTERVAL_MEM_LOAD (1<<6)
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#define IR_LIVE_INTERVAL_REG_LOAD (1<<7)
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#define IR_LIVE_INTERVAL_SPILL_SPECIAL (1<<8) /* spill slot is pre-allocated in a special area (see ir_ctx.spill_reserved_base) */
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#define IR_LIVE_INTERVAL_SPILLED (1<<9)
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struct _ir_live_interval {
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uint8_t type;
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int8_t reg;
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uint16_t flags;
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union {
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int32_t vreg;
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int32_t tmp_ref;
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};
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union {
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int32_t stack_spill_pos;
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ir_ref tmp_op_num;
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};
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ir_live_range range;
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ir_live_pos end; /* end of the last live range (cahce of ival.range.{next->}end) */
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ir_live_range *current_range;
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ir_use_pos *use_pos;
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ir_live_interval *top;
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ir_live_interval *next;
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ir_live_interval *list_next; /* linked list of active, inactive or unhandled intervals */
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};
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typedef int (*emit_copy_t)(ir_ctx *ctx, uint8_t type, ir_ref from, ir_ref to);
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int ir_gen_dessa_moves(ir_ctx *ctx, uint32_t b, emit_copy_t emit_copy);
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#if defined(IR_REGSET_64BIT)
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/*** Register Sets ***/
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#if IR_REGSET_64BIT
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typedef uint64_t ir_regset;
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#else
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typedef uint32_t ir_regset;
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#endif
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#define IR_REGSET_EMPTY 0
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#define IR_REGSET_IS_EMPTY(regset) \
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(regset == IR_REGSET_EMPTY)
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#define IR_REGSET_IS_SINGLETON(regset) \
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(regset && !(regset & (regset - 1)))
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#if IR_REGSET_64BIT
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# define IR_REGSET(reg) \
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(1ull << (reg))
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#else
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# define IR_REGSET(reg) \
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(1u << (reg))
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#endif
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#if IR_REGSET_64BIT
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# define IR_REGSET_INTERVAL(reg1, reg2) \
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(((1ull << ((reg2) - (reg1) + 1)) - 1) << (reg1))
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#else
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# define IR_REGSET_INTERVAL(reg1, reg2) \
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(((1u << ((reg2) - (reg1) + 1)) - 1) << (reg1))
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#endif
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#define IR_REGSET_IN(regset, reg) \
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(((regset) & IR_REGSET(reg)) != 0)
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#define IR_REGSET_INCL(regset, reg) \
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(regset) |= IR_REGSET(reg)
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#define IR_REGSET_EXCL(regset, reg) \
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(regset) &= ~IR_REGSET(reg)
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#define IR_REGSET_UNION(set1, set2) \
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((set1) | (set2))
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#define IR_REGSET_INTERSECTION(set1, set2) \
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((set1) & (set2))
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#define IR_REGSET_DIFFERENCE(set1, set2) \
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((set1) & ~(set2))
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#if IR_REGSET_64BIT
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# define IR_REGSET_FIRST(set) ((ir_reg)ir_ntzl(set))
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# define ir_REGSET_LAST(set) ((ir_reg)(ir_nlzl(set)(set)^63))
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#else
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# define IR_REGSET_FIRST(set) ((ir_reg)ir_ntz(set))
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# define IR_REGSET_LAST(set) ((ir_reg)(ir_nlz(set)^31))
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#endif
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#define IR_REGSET_FOREACH(set, reg) \
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do { \
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ir_regset _tmp = (set); \
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while (!IR_REGSET_IS_EMPTY(_tmp)) { \
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ir_reg _reg = IR_REGSET_FIRST(_tmp); \
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IR_REGSET_EXCL(_tmp, _reg); \
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reg = _reg; \
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#define IR_REGSET_FOREACH_END() \
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} \
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} while (0)
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/*** IR Register Allocation ***/
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/* Flags for ctx->regs[][] (low bits are used for register number itself) */
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typedef struct _ir_reg_alloc_data {
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int32_t stack_frame_size;
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int32_t unused_slot_4;
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int32_t unused_slot_2;
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int32_t unused_slot_1;
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} ir_reg_alloc_data;
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int32_t ir_allocate_spill_slot(ir_ctx *ctx, ir_type type, ir_reg_alloc_data *data);
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IR_ALWAYS_INLINE void ir_set_alocated_reg(ir_ctx *ctx, ir_ref ref, int op_num, int8_t reg)
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{
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int8_t *regs = ctx->regs[ref];
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if (op_num > 0) {
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/* regs[] is not limited by the declared boundary 4, the real boundary checked below */
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IR_ASSERT(op_num <= IR_MAX(3, ir_input_edges_count(ctx, &ctx->ir_base[ref])));
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}
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regs[op_num] = reg;
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}
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IR_ALWAYS_INLINE int8_t ir_get_alocated_reg(const ir_ctx *ctx, ir_ref ref, int op_num)
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{
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int8_t *regs = ctx->regs[ref];
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/* regs[] is not limited by the declared boundary 4, the real boundary checked below */
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IR_ASSERT(op_num <= IR_MAX(3, ir_input_edges_count(ctx, &ctx->ir_base[ref])));
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return regs[op_num];
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}
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/*** IR Target Interface ***/
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/* ctx->rules[] flags */
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#define IR_FUSED (1U<<31) /* Insn is fused into others (code is generated as part of the fusion root) */
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#define IR_SKIPPED (1U<<30) /* Insn is skipped (code is not generated) */
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#define IR_SIMPLE (1U<<29) /* Insn doesn't have any target constraints */
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#define IR_RULE_MASK 0xff
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typedef enum _ir_reg ir_reg;
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typedef struct _ir_target_constraints ir_target_constraints;
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#define IR_TMP_REG(_num, _type, _start, _end) \
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(ir_tmp_reg){.num=(_num), .type=(_type), .start=(_start), .end=(_end)}
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#define IR_SCRATCH_REG(_reg, _start, _end) \
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(ir_tmp_reg){.reg=(_reg), .type=IR_VOID, .start=(_start), .end=(_end)}
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int ir_get_target_constraints(const ir_ctx *ctx, ir_ref ref, ir_target_constraints *constraints);
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#endif /* defined(IR_REGSET_64BIT) */
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#endif /* IR_PRIVATE_H */
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