mirror of
https://github.com/danog/ir.git
synced 2024-11-27 04:45:38 +01:00
153 lines
3.4 KiB
C
153 lines
3.4 KiB
C
#include "ir.h"
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#if defined(IR_TARGET_X86) || defined(IR_TARGET_X64)
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# include "ir_x86.h"
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#elif defined(IR_TARGET_AARCH64)
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# include "ir_aarch64.h"
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#else
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# error "Unknown IR target"
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#endif
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#include "ir_private.h"
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#include <dlfcn.h>
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#define DASM_M_GROW(ctx, t, p, sz, need) \
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do { \
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size_t _sz = (sz), _need = (need); \
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if (_sz < _need) { \
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if (_sz < 16) _sz = 16; \
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while (_sz < _need) _sz += _sz; \
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(p) = (t *)ir_mem_realloc((p), _sz); \
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(sz) = _sz; \
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} \
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} while(0)
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#define DASM_M_FREE(ctx, p, sz) ir_mem_free(p)
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#if IR_DEBUG
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# define DASM_CHECKS
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#endif
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#if defined(__GNUC__)
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# pragma GCC diagnostic ignored "-Warray-bounds"
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#endif
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typedef struct _ir_copy {
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ir_type type;
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ir_reg from;
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ir_reg to;
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} ir_copy;
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IR_ALWAYS_INLINE uint32_t ir_rule(ir_ctx *ctx, ir_ref ref)
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{
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IR_ASSERT(!IR_IS_CONST_REF(ref));
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return ctx->rules[ref];
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}
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static bool ir_is_same_mem(ir_ctx *ctx, ir_ref r1, ir_ref r2)
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{
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ir_live_interval *ival1, *ival2;
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int32_t o1, o2;
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if (IR_IS_CONST_REF(r1) || IR_IS_CONST_REF(r2)) {
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return 0;
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}
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IR_ASSERT(ctx->vregs[r1] && ctx->vregs[r2]);
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ival1 = ctx->live_intervals[ctx->vregs[r1]];
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ival2 = ctx->live_intervals[ctx->vregs[r2]];
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IR_ASSERT(ival1 && ival2);
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o1 = ival1->stack_spill_pos;
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o2 = ival2->stack_spill_pos;
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IR_ASSERT(o1 != -1 && o2 != -1);
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return o1 == o2;
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}
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static void *ir_resolve_sym_name(const char *name)
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{
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void *handle = NULL;
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void *addr;
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#ifdef RTLD_DEFAULT
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handle = RTLD_DEFAULT;
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#endif
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addr = dlsym(handle, name);
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IR_ASSERT(addr != NULL);
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return addr;
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}
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#ifdef IR_SNAPSHOT_HANDLER_DCL
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IR_SNAPSHOT_HANDLER_DCL();
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#endif
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static void *ir_jmp_addr(ir_ctx *ctx, ir_insn *insn, ir_insn *addr_insn)
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{
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void *addr;
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IR_ASSERT(addr_insn->type == IR_ADDR);
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if (addr_insn->op == IR_FUNC) {
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addr = ir_resolve_sym_name(ir_get_str(ctx, addr_insn->val.addr));
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} else {
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IR_ASSERT(addr_insn->op == IR_ADDR || addr_insn->op == IR_FUNC_ADDR);
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addr = (void*)addr_insn->val.addr;
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}
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#ifdef IR_SNAPSHOT_HANDLER
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if (ctx->ir_base[insn->op1].op == IR_SNAPSHOT) {
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addr = IR_SNAPSHOT_HANDLER(ctx, insn->op1, &ctx->ir_base[insn->op1], addr);
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}
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#endif
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return addr;
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}
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#if defined(IR_TARGET_X86) || defined(IR_TARGET_X64)
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# include "dynasm/dasm_proto.h"
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# include "dynasm/dasm_x86.h"
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# include "ir_emit_x86.h"
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#elif defined(IR_TARGET_AARCH64)
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# include "dynasm/dasm_proto.h"
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# include "dynasm/dasm_arm64.h"
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# include "ir_emit_aarch64.h"
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#else
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# error "Unknown IR target"
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#endif
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int ir_match(ir_ctx *ctx)
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{
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int b, n;
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ir_ref i;
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ir_block *bb;
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ir_insn *insn;
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if (!ctx->prev_insn_len) {
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ctx->prev_insn_len = ir_mem_malloc(ctx->insns_count * sizeof(uint32_t));
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n = 1;
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for (b = 1, bb = ctx->cfg_blocks + b; b <= ctx->cfg_blocks_count; b++, bb++) {
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if (bb->flags & IR_BB_UNREACHABLE) {
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continue;
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}
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for (i = bb->start, insn = ctx->ir_base + i; i <= bb->end;) {
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ctx->prev_insn_len[i] = n;
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n = ir_operands_count(ctx, insn);
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n = 1 + (n >> 2); // support for multi-word instructions like MERGE and PHI
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i += n;
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insn += n;
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}
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}
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}
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ctx->rules = ir_mem_calloc(ctx->insns_count, sizeof(uint32_t));
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for (b = ctx->cfg_blocks_count, bb = ctx->cfg_blocks + b; b > 0; b--, bb--) {
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if (bb->flags & IR_BB_UNREACHABLE) {
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continue;
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}
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for (i = bb->end; i >= bb->start; i -= ctx->prev_insn_len[i]) {
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insn = &ctx->ir_base[i];
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if (!ctx->rules[i]) {
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ctx->rules[i] = ir_match_insn(ctx, i, bb);
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}
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}
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}
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return 1;
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}
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