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{"version":3,"file":"3420.3a5367f73895e3c3c1f4.js","mappings":"sFAsNAA,EAAOC,QA9MP,SAAcC,GA8KZ,MAAO,CACLC,KAAM,OACNC,kBAAkB,EAClBC,SAAU,CACRC,QArKa,CACf,MACA,SACA,QACA,QACA,MACA,MACA,eACA,QACA,SACA,SACA,mBACA,YACA,QACA,QACA,OACA,SACA,MACA,OACA,YACA,gBACA,WACA,UACA,QACA,aACA,SACA,UACA,OACA,QACA,MACA,SACA,OACA,WACA,OACA,MACA,QACA,WACA,WACA,UACA,QACA,UACA,KACA,SACA,KACA,WACA,QACA,KACA,QACA,UACA,UACA,UACA,OACA,MACA,MACA,OACA,MACA,OACA,MACA,MACA,OACA,KACA,KACA,OACA,KACA,SACA,MACA,UACA,YACA,OACA,YACA,YACA,UACA,WACA,YACA,OACA,QACA,SACA,WACA,SACA,UACA,MACA,SACA,WACA,qBACA,SACA,MACA,MACA,SACA,WACA,WACA,SACA,SACA,MACA,MACA,MACA,MACA,SACA,UACA,OACA,KACA,YACA,OACA,aACA,QACA,QACA,MACA,WACA,OACA,QACA,QACA,QACA,OACA,OACA,QACA,OACA,OACA,OAkDEC,SAhDc,CAChB,UACA,MACA,YACA,UACA,OACA,eACA,UACA,WACA,SACA,aACA,iBACA,mBACA,YACA,mBACA,WACA,SACA,iBACA,iBACA,aACA,oBACA,sBACA,aACA,oBACA,WACA,cACA,eAuBEC,QArBa,CAEf,QACA,OACA,OACA,UACA,QACA,UAEA,OACA,OACA,OACA,UAWAC,QAAS,KACTC,SAAU,CACRR,EAAKS,qBACLT,EAAKU,QAAQ,KAAM,KACnBV,EAAKW,kBACL,CACEC,UAAW,SACXC,MAlLY,8GAmLZC,UAAW,GAEb,CACEF,UAAW,SACXC,MAAO,wBACPL,SAAU,CAAER,EAAKe,mBAEnB,CACEH,UAAW,SACXC,MAAO,4BACPL,SAAU,CAAER,EAAKe","sources":["webpack://telegram-t/./node_modules/highlight.js/lib/languages/vhdl.js"],"sourcesContent":["/*\nLanguage: VHDL\nAuthor: Igor Kalnitsky <igor@kalnitsky.org>\nContributors: Daniel C.K. Kho <daniel.kho@tauhop.com>, Guillaume Savaton <guillaume.savaton@eseo.fr>\nDescription: VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems.\nWebsite: https://en.wikipedia.org/wiki/VHDL\n*/\n\nfunction vhdl(hljs) {\n // Regular expression for VHDL numeric literals.\n\n // Decimal literal:\n const INTEGER_RE = '\\\\d(_|\\\\d)*';\n const EXPONENT_RE = '[eE][-+]?' + INTEGER_RE;\n const DECIMAL_LITERAL_RE = INTEGER_RE + '(\\\\.' + INTEGER_RE + ')?' + '(' + EXPONENT_RE + ')?';\n // Based literal:\n const BASED_INTEGER_RE = '\\\\w+';\n const BASED_LITERAL_RE = INTEGER_RE + '#' + BASED_INTEGER_RE + '(\\\\.' + BASED_INTEGER_RE + ')?' + '#' + '(' + EXPONENT_RE + ')?';\n\n const NUMBER_RE = '\\\\b(' + BASED_LITERAL_RE + '|' + DECIMAL_LITERAL_RE + ')';\n\n const KEYWORDS = [\n \"abs\",\n \"access\",\n \"after\",\n \"alias\",\n \"all\",\n \"and\",\n \"architecture\",\n \"array\",\n \"assert\",\n \"assume\",\n \"assume_guarantee\",\n \"attribute\",\n \"begin\",\n \"block\",\n \"body\",\n \"buffer\",\n \"bus\",\n \"case\",\n \"component\",\n \"configuration\",\n \"constant\",\n \"context\",\n \"cover\",\n \"disconnect\",\n \"downto\",\n \"default\",\n \"else\",\n \"elsif\",\n \"end\",\n \"entity\",\n \"exit\",\n \"fairness\",\n \"file\",\n \"for\",\n \"force\",\n \"function\",\n \"generate\",\n \"generic\",\n \"group\",\n \"guarded\",\n \"if\",\n \"impure\",\n \"in\",\n \"inertial\",\n \"inout\",\n \"is\",\n \"label\",\n \"library\",\n \"linkage\",\n \"literal\",\n \"loop\",\n \"map\",\n \"mod\",\n \"nand\",\n \"new\",\n \"next\",\n \"nor\",\n \"not\",\n \"null\",\n \"of\",\n \"on\",\n \"open\",\n \"or\",\n \"others\",\n \"out\",\n \"package\",\n \"parameter\",\n \"port\",\n \"postponed\",\n \"procedure\",\n \"process\",\n \"property\",\n \"protected\",\n \"pure\",\n \"range\",\n \"record\",\n \"register\",\n \"reject\",\n \"release\",\n \"rem\",\n \"report\",\n \"restrict\",\n \"restrict_guarantee\",\n \"return\",\n \"rol\",\n \"ror\",\n \"select\",\n \"sequence\",\n \"severity\",\n \"shared\",\n \"signal\",\n \"sla\",\n \"sll\",\n \"sra\",\n \"srl\",\n \"strong\",\n \"subtype\",\n \"then\",\n \"to\",\n \"transport\",\n \"type\",\n \"unaffected\",\n \"units\",\n \"until\",\n \"use\",\n \"variable\",\n \"view\",\n \"vmode\",\n \"vprop\",\n \"vunit\",\n \"wait\",\n \"when\",\n \"while\",\n
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