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This highlighter supports Verilog and SystemVerilog through IEEE 1800-2012.\nWebsite: http://www.verilog.com\n*/\n\nfunction verilog(hljs) {\n  const regex = hljs.regex;\n  const KEYWORDS = {\n    $pattern: /\\$?[\\w]+(\\$[\\w]+)*/,\n    keyword: [\n      \"accept_on\",\n      \"alias\",\n      \"always\",\n      \"always_comb\",\n      \"always_ff\",\n      \"always_latch\",\n      \"and\",\n      \"assert\",\n      \"assign\",\n      \"assume\",\n      \"automatic\",\n      \"before\",\n      \"begin\",\n      \"bind\",\n      \"bins\",\n      \"binsof\",\n      \"bit\",\n      \"break\",\n      \"buf|0\",\n      \"bufif0\",\n      \"bufif1\",\n      \"byte\",\n      \"case\",\n      \"casex\",\n      \"casez\",\n      \"cell\",\n      \"chandle\",\n      \"checker\",\n      \"class\",\n      \"clocking\",\n      \"cmos\",\n      \"config\",\n      \"const\",\n      \"constraint\",\n      \"context\",\n      \"continue\",\n      \"cover\",\n      \"covergroup\",\n      \"coverpoint\",\n      \"cross\",\n      \"deassign\",\n      \"default\",\n      \"defparam\",\n      \"design\",\n      \"disable\",\n      \"dist\",\n      \"do\",\n      \"edge\",\n      \"else\",\n      \"end\",\n      \"endcase\",\n      \"endchecker\",\n      \"endclass\",\n      \"endclocking\",\n      \"endconfig\",\n      \"endfunction\",\n      \"endgenerate\",\n      \"endgroup\",\n      \"endinterface\",\n      \"endmodule\",\n      \"endpackage\",\n      \"endprimitive\",\n      \"endprogram\",\n      \"endproperty\",\n      \"endspecify\",\n      \"endsequence\",\n      \"endtable\",\n      \"endtask\",\n      \"enum\",\n      \"event\",\n      \"eventually\",\n      \"expect\",\n      \"export\",\n      \"extends\",\n      \"extern\",\n      \"final\",\n      \"first_match\",\n      \"for\",\n      \"force\",\n      \"foreach\",\n      \"forever\",\n      \"fork\",\n      \"forkjoin\",\n      \"function\",\n      \"generate|5\",\n      \"genvar\",\n      \"global\",\n      \"highz0\",\n      \"highz1\",\n      \"if\",\n      \"iff\",\n      \"ifnone\",\n      \"ignore_bins\",\n      \"illegal_bins\",\n      \"implements\",\n      \"implies\",\n      \"import\",\n      \"incdir\",\n      \"include\",\n      \"initial\",\n      \"inout\",\n      \"input\",\n      \"inside\",\n      \"instance\",\n      \"int\",\n      \"integer\",\n      \"interconnect\",\n      \"interface\",\n      \"intersect\",\n      \"join\",\n      \"join_any\",\n      \"join_none\",\n      \"large\",\n      \"let\",\n      \"liblist\",\n      \"library\",\n      \"local\",\n      \"localparam\",\n      \"logic\",\n      \"longint\",\n      \"macromodule\",\n      \"matches\",\n      \"medium\",\n      \"modport\",\n      \"module\",\n      \"nand\",\n      \"negedge\",\n      \"nettype\",\n      \"new\",\n      \"nexttime\",\n      \"nmos\",\n      \"nor\",\n      \"noshowcancelled\",\n      \"not\",\n      \"notif0\",\n      \"notif1\",\n      \"or\",\n      \"output\",\n      \"package\",\n      \"packed\",\n      \"parameter\",\n      \"pmos\",\n      \"posedge\",\n      \"primitive\",\n      \"priority\",\n      \"program\",\n      \"property\",\n      \"protected\",\n      \"pull0\",\n      \"pull1\",\n      \"pulldown\",\n      \"pullup\",\n      \"pulsestyle_ondetect\",\n      \"pulsestyle_onevent\",\n      \"pure\",\n      \"rand\",\n      \"randc\",\n      \"randcase\",\n      \"randsequence\",\n      \"rcmos\",\n      \"real\",\n      \"realtime\",\n      \"ref\",\n      \"reg\",\n      \"reject_on\",\n      \"release\",\n      \"repeat\",\n      \"restrict\",\n      \"return\",\n      \"rnmos\",\n      \"rpmos\",\n      \"rtran\",\n      \"rtranif0\",\n      \"rtranif1\",\n      \"s_always\",\n      \"s_eventually\",\n      \"s_nexttime\",\n      \"s_until\",\n      \"s_until_with\",\n      \"scalared\",\n      \"sequence\",\n      \"shortint\",\n      \"shortreal\",\n      \"showcancelled\",\n      \"signed\",\n      \"small\",\n      \"soft\",\n      \"solve\",\n      \"specify\",\n      \"specparam\",\n      \"static\",\n      \"string\",\n      \"strong\",\n      \"strong0\",\n      \"strong1\",\n      \"struct\",\n      \"super\",\n      \"supply0\",\n      \"supply1\",\n      \"sync_accept_on\",\n      \"sync_reject_on\",\n      \"table\",\n      \"tagged\",\n      \"task\",\n      \"this\",\n      \"throughout\",\n      \"time\",\n      \"timeprecision\",\n      \"timeunit\",\n      \"tran\",\n      \"tranif0\",\n      \"tranif1\",\n      \"tri\",\n      \"tri0\",\n      \"tri1\",\n      \"triand\",\n      \"trior\",\n      \"trireg\",\n      \"type\",\n      \"typedef\",\n      \"union\",\n      \"unique\",\n      \"unique0\",\n      \"unsigned\",\n      \"until\",\n      \"until_with\",\n      \"untyped\",\n      \"use\",\n      \"uwire\",\n      \"var\",\n      \"vectored\",\n      \"virtual\",\n      \"void\",\n      \"wait\",\n      \"wait_order\",\n      \"wand\",\n      \"weak\",\n      \"weak0\",\n      \"weak1\",\n      \"while\",\n      \"wildcard\",\n      \"wire\",\n      \"with\",\n      \"within\",\n      \"wor\",\n      \"xnor\",\n      \"xor\"\n    ],\n    literal: [ 'null' ],\n    built_in: [\n      \"$finish\",\n      \"$stop\",\n      \"$exit\",\n      \"$fatal\",\n      \"$error\",\n      \"$warning\",\n      \"$info\",\n      \"$realtime\",\n      \"$time\",\n      \"$printtimescale\",\n      \"$bitstoreal\",\n      \"$bitstoshortreal\",\n      \"$itor\",\n      \"$signed\",\n      \"$cast\",\n      \"$bits\",\n      \"$stime\",\n      \"$timeformat\",\n      \"$realtobits\",\n      \"$shortrealtobits\",\n      \"$rtoi\",\n      \"$unsigned\",\n      \"$asserton\",\n      \"$assertkill\",\n      \"$assertpasson\",\n      \"$assertfailon\",\n      \"$assertnonvacuouson\",\n      \"$assertoff\",\n      \"$assertcontrol\",\n      \"$assertpassoff\",\n      \"$assertfailoff\",\n      \"$assertvacuousoff\",\n      \"$isunbounded\",\n      \"$sampled\",\n      \"$fell\",\n      \"$changed\",\n      \"$past_gclk\",\n      \"$fell_gclk\",\n      \"$changed_gclk\",\n      \"$rising_gclk\",\n      \"$steady_gclk\",\n      \"$coverage_control\",\n      \"$coverage_get\",\n      \"$coverage_save\",\n      \"$set_coverage_db_name\",\n      \"$rose\",\n      \"$stable\",\n      \"$past\",\n      \"$rose_gclk\",\n      \"$stable_gclk\",\n      \"$future_gclk\",\n      \"$falling_gclk\",\n      \"$changing_gclk\",\n      \"$display\",\n      \"$coverage_get_max\",\n      \"$coverage_merge\",\n      \"$get_coverage\",\n      \"$load_coverage_db\",\n      \"$typename\",\n      \"$unpacked_dimensions\",\n      \"$left\",\n      \"$low\",\n      \"$increment\",\n      \"$clog2\",\n      \"$ln\",\n      \"$log10\",\n      \"$exp\",\n      \"$sqrt\",\n      \"$pow\",\n      \"$floor\",\n      \"$ceil\",\n      \"$sin\",\n      \"$cos\",\n      \"$tan\",\n      \"$countbits\",\n      \"$onehot\",\n      \"$isunknown\",\n      \"$fatal\",\n      \"$warning\",\n      \"$dimensions\",\n      \"$right\",\n      \"$high\",\n      \"$size\",\n      \"$asin\",\n      \"$acos\",\n      \"$atan\",\n      \"$atan2\",\n      \"$hypot\",\n      \"$sinh\",\n      \"$cosh\",\n      \"$tanh\",\n      \"$asinh\",\n      \"$acosh\",\n      \"$atanh\",\n      \"$countones\",\n      \"$onehot0\",\n      \"$error\",\n      \"$info\",\n      \"$random\",\n      \"$dist_chi_square\",\n      \"$dist_erlang\",\n      \"$dist_exponential\",\n      \"$dist_normal\",\n      \"$dist_poisson\",\n      \"$dist_t\",\n      \"$dist_uniform\",\n      \"$q_initialize\",\n      \"$q_remove\",\n      \"$q_exam\",\n      \"$async$and$array\",\n      \"$async$nand$array\",\n      \"$async$or$array\",\n      \"$async$nor$array\",\n      \"$sync$and$array\",\n      \"$sync$nand$array\",\n      \"$sync$or$array\",\n      \"$sync$nor$array\",\n      \"$q_add\",\n      \"$q_full\",\n      \"$psprintf\",\n      \"$async$and$plane\",\n      \"$async$nand$plane\",\n      \"$async$or$plane\",\n      \"$async$nor$plane\",\n      \"$sync$and$plane\",\n      \"$sync$nand$plane\",\n      \"$sync$or$plane\",\n      \"$sync$nor$plane\",\n      \"$system\",\n      \"$display\",\n      \"$displayb\",\n      \"$displayh\",\n      \"$displayo\",\n      \"$strobe\",\n      \"$strobeb\",\n      \"$strobeh\",\n      \"$strobeo\",\n      \"$write\",\n      \"$readmemb\",\n      \"$readmemh\",\n      \"$writememh\",\n      \"$value$plusargs\",\n      \"$dumpvars\",\n      \"$dumpon\",\n      \"$dumplimit\",\n      \"$dumpports\",\n      \"$dumpportson\",\n      \"$dumpportslimit\",\n      \"$writeb\",\n      \"$writeh\",\n      \"$writeo\",\n      \"$monitor\",\n      \"$monitorb\",\n      \"$monitorh\",\n      \"$monitoro\",\n      \"$writememb\",\n      \"$dumpfile\",\n      \"$dumpoff\",\n      \"$dumpall\",\n      \"$dumpflush\",\n      \"$dumpportsoff\",\n      \"$dumpportsall\",\n      \"$dumpportsflush\",\n      \"$fclose\",\n      \"$fdisplay\",\n      \"$fdisplayb\",\n      \"$fdisplayh\",\n      \"$fdisplayo\",\n      \"$fstrobe\",\n      \"$fstrobeb\",\n      \"$fstrobeh\",\n      \"$fstrobeo\",\n      \"$swrite\",\n      \"$swriteb\",\n      \"$swriteh\",\n      \"$swriteo\",\n      \"$fscanf\",\n      \"$fread\",\n      \"$fseek\",\n      \"$fflush\",\n      \"$feof\",\n      \"$fopen\",\n      \"$fwrite\",\n      \"$fwriteb\",\n      \"$fwriteh\",\n      \"$fwriteo\",\n      \"$fmonitor\",\n      \"$fmonitorb\",\n      \"$fmonitorh\",\n      \"$fmonitoro\",\n      \"$sformat\",\n      \"$sformatf\",\n      \"$fgetc\",\n      \"$ungetc\",\n      \"$fgets\",\n      \"$sscanf\",\n      \"$rewind\",\n      \"$ftell\",\n      \"$ferror\"\n    ]\n  };\n  const BUILT_IN_CONSTANTS = [\n    \"__FILE__\",\n    \"__LINE__\"\n  ];\n  const DIRECTIVES = [\n    \"begin_keywords\",\n    \"celldefine\",\n    \"default_nettype\",\n    \"default_decay_time\",\n    \"default_trireg_strength\",\n    \"define\",\n    \"delay_mode_distributed\",\n    \"delay_mode_path\",\n    \"delay_mode_unit\",\n    \"delay_mode_zero\",\n    \"else\",\n    \"elsif\",\n    \"end_keywords\",\n    \"endcelldefine\",\n    \"endif\",\n    \"ifdef\",\n    \"ifndef\",\n    \"include\",\n    \"line\",\n    \"nounconnected_drive\",\n    \"pragma\",\n    \"resetall\",\n    \"timescale\",\n    \"unconnected_drive\",\n    \"undef\",\n    \"undefineall\"\n  ];\n\n  return {\n    name: 'Verilog',\n    aliases: [\n      'v',\n      'sv',\n      'svh'\n    ],\n    case_insensitive: false,\n    keywords: KEYWORDS,\n    contains: [\n      hljs.C_BLOCK_COMMENT_MODE,\n      hljs.C_LINE_COMMENT_MODE,\n      hljs.QUOTE_STRING_MODE,\n      {\n        scope: 'number',\n        contains: [ hljs.BACKSLASH_ESCAPE ],\n        variants: [\n          { begin: /\\b((\\d+'([bhodBHOD]))[0-9xzXZa-fA-F_]+)/ },\n          { begin: /\\B(('([bhodBHOD]))[0-9xzXZa-fA-F_]+)/ },\n          { // decimal\n            begin: /\\b[0-9][0-9_]*/,\n            relevance: 0\n          }\n        ]\n      },\n      /* parameters to instances */\n      {\n        scope: 'variable',\n        variants: [\n          { begin: '#\\\\((?!parameter).+\\\\)' },\n          {\n            begin: '\\\\.\\\\w+',\n            relevance: 0\n          }\n        ]\n      },\n      {\n        scope: 'variable.constant',\n        match: regex.concat(/`/, regex.either(...BUILT_IN_CONSTANTS)),\n      },\n      {\n        scope: 'meta',\n        begin: regex.concat(/`/, regex.either(...DIRECTIVES)),\n        end: /$|\\/\\/|\\/\\*/,\n        returnEnd: true,\n        keywords: DIRECTIVES\n      }\n    ]\n  };\n}\n\nmodule.exports = verilog;\n"],"names":["module","exports","hljs","regex","DIRECTIVES","name","aliases","case_insensitive","keywords","$pattern","keyword","literal","built_in","contains","C_BLOCK_COMMENT_MODE","C_LINE_COMMENT_MODE","QUOTE_STRING_MODE","scope","BACKSLASH_ESCAPE","variants","begin","relevance","match","concat","either","end","returnEnd"],"sourceRoot":""}