2022-11-08 09:32:46 +01:00
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/*
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* IR - Lightweight JIT Compilation Framework
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* (CFG - Control Flow Graph)
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* Copyright (C) 2022 Zend by Perforce.
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* Authors: Dmitry Stogov <dmitry@php.net>
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*/
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2022-04-05 23:19:23 +02:00
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#include "ir.h"
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#include "ir_private.h"
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2022-11-11 08:25:59 +01:00
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static ir_ref _ir_merge_blocks(ir_ctx *ctx, ir_ref end, ir_ref begin)
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2022-10-05 15:29:49 +02:00
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{
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ir_ref prev, next;
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ir_use_list *use_list;
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2022-11-11 08:25:59 +01:00
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ir_ref n, *p;
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2022-10-05 15:29:49 +02:00
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IR_ASSERT(ctx->ir_base[begin].op == IR_BEGIN);
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IR_ASSERT(ctx->ir_base[end].op == IR_END);
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IR_ASSERT(ctx->ir_base[begin].op1 == end);
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IR_ASSERT(ctx->use_lists[end].count == 1);
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prev = ctx->ir_base[end].op1;
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use_list = &ctx->use_lists[begin];
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IR_ASSERT(use_list->count == 1);
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next = ctx->use_edges[use_list->refs];
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/* remove BEGIN and END */
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ctx->ir_base[begin].op = IR_NOP;
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ctx->ir_base[begin].op1 = IR_UNUSED;
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ctx->use_lists[begin].count = 0;
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ctx->ir_base[end].op = IR_NOP;
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ctx->ir_base[end].op1 = IR_UNUSED;
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ctx->use_lists[end].count = 0;
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/* connect their predecessor and successor */
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ctx->ir_base[next].op1 = prev;
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use_list = &ctx->use_lists[prev];
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n = use_list->count;
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2022-11-11 08:25:59 +01:00
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for (p = &ctx->use_edges[use_list->refs]; n > 0; p++, n--) {
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2022-10-05 15:29:49 +02:00
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if (*p == end) {
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*p = next;
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}
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}
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return next;
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}
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2022-11-09 19:56:31 +01:00
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IR_ALWAYS_INLINE void _ir_add_successors(ir_ctx *ctx, ir_ref ref, ir_worklist *worklist)
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{
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ir_use_list *use_list = &ctx->use_lists[ref];
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ir_ref *p, use, n = use_list->count;
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if (n < 2) {
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if (n == 1) {
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use = ctx->use_edges[use_list->refs];
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IR_ASSERT(ir_op_flags[ctx->ir_base[use].op] & IR_OP_FLAG_CONTROL);
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ir_worklist_push(worklist, use);
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}
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} else {
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p = &ctx->use_edges[use_list->refs];
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if (n == 2) {
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use = *p;
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IR_ASSERT(ir_op_flags[ctx->ir_base[use].op] & IR_OP_FLAG_CONTROL);
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ir_worklist_push(worklist, use);
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use = *(p + 1);
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IR_ASSERT(ir_op_flags[ctx->ir_base[use].op] & IR_OP_FLAG_CONTROL);
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ir_worklist_push(worklist, use);
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} else {
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for (; n > 0; p++, n--) {
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use = *p;
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IR_ASSERT(ir_op_flags[ctx->ir_base[use].op] & IR_OP_FLAG_CONTROL);
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ir_worklist_push(worklist, use);
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}
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}
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}
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}
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IR_ALWAYS_INLINE void _ir_add_predecessors(ir_insn *insn, ir_worklist *worklist)
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{
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2022-11-11 08:25:59 +01:00
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ir_ref n, *p, ref;
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2022-11-09 19:56:31 +01:00
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if (insn->op == IR_MERGE || insn->op == IR_LOOP_BEGIN) {
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n = ir_variable_inputs_count(insn);
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2022-11-11 08:25:59 +01:00
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for (p = insn->ops + 1; n > 0; p++, n--) {
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2022-11-09 19:56:31 +01:00
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ref = *p;
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IR_ASSERT(ref);
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ir_worklist_push(worklist, ref);
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}
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} else if (insn->op != IR_START && insn->op != IR_ENTRY) {
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2022-11-29 18:02:07 +01:00
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if (EXPECTED(insn->op1)) {
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ir_worklist_push(worklist, insn->op1);
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}
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2022-11-09 19:56:31 +01:00
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}
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}
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2022-04-05 23:19:23 +02:00
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int ir_build_cfg(ir_ctx *ctx)
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{
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2022-11-11 08:25:59 +01:00
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ir_ref n, *p, ref, start, end, next;
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2022-11-08 21:09:35 +01:00
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uint32_t b;
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2022-04-05 23:19:23 +02:00
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ir_insn *insn;
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ir_worklist worklist;
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2022-11-08 21:09:35 +01:00
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uint32_t count, bb_count = 0;
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2022-04-05 23:19:23 +02:00
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uint32_t edges_count = 0;
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ir_block *blocks, *bb;
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uint32_t *_blocks, *edges;
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2022-06-20 22:31:32 +02:00
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ir_use_list *use_list;
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2022-11-11 08:25:59 +01:00
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uint32_t len = ir_bitset_len(ctx->insns_count);
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ir_bitset bb_starts = ir_mem_calloc(len * 2, IR_BITSET_BITS / 8);
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ir_bitset bb_leaks = bb_starts + len;
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2022-06-20 22:31:32 +02:00
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_blocks = ir_mem_calloc(ctx->insns_count, sizeof(uint32_t));
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2022-04-05 23:19:23 +02:00
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ir_worklist_init(&worklist, ctx->insns_count);
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2022-11-11 08:25:59 +01:00
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/* First try to perform backward DFS search starting from "stop" nodes */
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2022-06-17 11:20:15 +02:00
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2022-06-20 22:31:32 +02:00
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/* Add all "stop" nodes */
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ref = ctx->ir_base[1].op1;
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2022-06-17 11:20:15 +02:00
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while (ref) {
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2022-06-20 22:31:32 +02:00
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ir_worklist_push(&worklist, ref);
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ref = ctx->ir_base[ref].op3;
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2022-06-17 11:20:15 +02:00
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}
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while (ir_worklist_len(&worklist)) {
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ref = ir_worklist_pop(&worklist);
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insn = &ctx->ir_base[ref];
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2022-11-11 08:25:59 +01:00
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IR_ASSERT(IR_IS_BB_END(insn->op));
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/* Remember BB end */
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end = ref;
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/* Some successors of IF and SWITCH nodes may be inaccessible by backward DFS */
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use_list = &ctx->use_lists[end];
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n = use_list->count;
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if (n > 1) {
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for (p = &ctx->use_edges[use_list->refs]; n > 0; p++, n--) {
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/* Remember possible inaccessible succcessors */
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ir_bitset_incl(bb_leaks, *p);
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}
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}
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/* Skip control nodes untill BB start */
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ref = insn->op1;
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while (1) {
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insn = &ctx->ir_base[ref];
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if (IR_IS_BB_START(insn->op)) {
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if (insn->op == IR_BEGIN
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&& (ctx->flags & IR_OPT_CFG)
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&& ctx->ir_base[insn->op1].op == IR_END
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&& ctx->use_lists[ref].count == 1) {
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ref = _ir_merge_blocks(ctx, insn->op1, ref);
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ref = ctx->ir_base[ref].op1;
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continue;
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2022-06-17 11:20:15 +02:00
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}
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2022-11-11 08:25:59 +01:00
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break;
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2022-06-17 11:20:15 +02:00
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}
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2022-11-11 08:25:59 +01:00
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ref = insn->op1; // follow connected control blocks untill BB start
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}
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/* Mark BB Start */
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bb_count++;
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_blocks[ref] = end;
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ir_bitset_incl(bb_starts, ref);
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/* Add predecessors */
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_ir_add_predecessors(insn, &worklist);
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}
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/* Backward DFS way miss some branches ending by infinite loops. */
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/* Try forward DFS. (in most cases all nodes are already proceed. */
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/* START node my be inaccessible from "stop" nodes */
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ir_bitset_incl(bb_leaks, 1);
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/* ENTRY nodes may be inaccessible from "stop" nodes */
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ref = ctx->ir_base[1].op2;
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while (ref) {
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ir_bitset_incl(bb_leaks, ref);
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ref = ctx->ir_base[ref].op2;
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}
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/* Add all not processed START, ENTRY and succcessor of IF and SWITCH */
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IR_BITSET_FOREACH_DIFFERENCE(bb_leaks, bb_starts, len, start) {
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ir_worklist_push(&worklist, start);
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} IR_BITSET_FOREACH_END();
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if (ir_worklist_len(&worklist)) {
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ir_bitset_union(worklist.visited, bb_starts, len);
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do {
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ref = ir_worklist_pop(&worklist);
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insn = &ctx->ir_base[ref];
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2022-06-20 22:31:32 +02:00
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IR_ASSERT(IR_IS_BB_START(insn->op));
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2022-11-11 08:25:59 +01:00
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/* Remember BB start */
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2022-11-10 20:45:12 +01:00
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start = ref;
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2022-06-20 22:31:32 +02:00
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/* Skip control nodes untill BB end */
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while (1) {
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2022-06-17 11:20:15 +02:00
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use_list = &ctx->use_lists[ref];
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n = use_list->count;
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2022-11-11 08:25:59 +01:00
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next = IR_UNUSED;
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for (p = &ctx->use_edges[use_list->refs]; n > 0; p++, n--) {
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next = *p;
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insn = &ctx->ir_base[next];
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if ((ir_op_flags[insn->op] & IR_OP_FLAG_CONTROL) && insn->op1 == ref) {
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2022-06-20 22:31:32 +02:00
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break;
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2022-06-17 11:20:15 +02:00
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}
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}
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2022-11-11 08:25:59 +01:00
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IR_ASSERT(next != IR_UNUSED);
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ref = next;
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2022-10-05 15:29:49 +02:00
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next_successor:
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2022-06-20 22:31:32 +02:00
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if (IR_IS_BB_END(insn->op)) {
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2022-10-05 15:29:49 +02:00
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if (insn->op == IR_END && (ctx->flags & IR_OPT_CFG)) {
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use_list = &ctx->use_lists[ref];
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IR_ASSERT(use_list->count == 1);
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next = ctx->use_edges[use_list->refs];
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if (ctx->ir_base[next].op == IR_BEGIN
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&& ctx->use_lists[next].count == 1) {
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2022-11-11 08:25:59 +01:00
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ref = _ir_merge_blocks(ctx, ref, next);
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2022-10-05 15:29:49 +02:00
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insn = &ctx->ir_base[ref];
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goto next_successor;
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}
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}
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2022-06-20 22:31:32 +02:00
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break;
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}
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}
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2022-11-11 08:25:59 +01:00
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/* Mark BB Start */
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bb_count++;
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2022-11-10 20:45:12 +01:00
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_blocks[start] = ref;
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2022-11-11 08:25:59 +01:00
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ir_bitset_incl(bb_starts, start);
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2022-06-20 22:31:32 +02:00
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/* Add successors */
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2022-11-09 19:56:31 +01:00
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_ir_add_successors(ctx, ref, &worklist);
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2022-11-11 08:25:59 +01:00
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} while (ir_worklist_len(&worklist));
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2022-06-17 11:20:15 +02:00
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}
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2022-11-10 20:45:12 +01:00
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ir_worklist_clear(&worklist);
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2022-06-17 11:20:15 +02:00
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2022-11-10 20:45:12 +01:00
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IR_ASSERT(bb_count > 0);
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2022-06-17 08:41:06 +02:00
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2022-11-10 22:19:17 +01:00
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/* Create array of basic blocks and count succcessor/predecessors edges for each BB */
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blocks = ir_mem_malloc((bb_count + 1) * sizeof(ir_block));
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2022-11-10 20:45:12 +01:00
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b = 1;
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bb = blocks + 1;
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2022-11-10 22:19:17 +01:00
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count = 0;
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2022-11-11 08:25:59 +01:00
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IR_BITSET_FOREACH(bb_starts, len, start) {
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2022-11-10 20:45:12 +01:00
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end = _blocks[start];
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_blocks[start] = b;
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_blocks[end] = b;
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2022-11-10 22:19:17 +01:00
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insn = &ctx->ir_base[start];
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IR_ASSERT(IR_IS_BB_START(insn->op));
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IR_ASSERT(end > start);
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2022-11-10 20:45:12 +01:00
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bb->start = start;
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bb->end = end;
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2022-11-10 22:19:17 +01:00
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bb->successors = count;
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count += ctx->use_lists[end].count;
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bb->successors_count = 0;
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bb->predecessors = count;
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bb->dom_parent = 0;
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bb->dom_depth = 0;
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bb->dom_child = 0;
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bb->dom_next_child = 0;
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bb->loop_header = 0;
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bb->loop_depth = 0;
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2022-06-20 15:34:44 +02:00
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if (insn->op == IR_START) {
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2022-11-10 22:19:17 +01:00
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bb->flags = IR_BB_START;
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bb->predecessors_count = 0;
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2022-06-20 15:34:44 +02:00
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ir_worklist_push(&worklist, b);
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} else if (insn->op == IR_ENTRY) {
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2022-11-10 22:19:17 +01:00
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bb->flags = IR_BB_ENTRY;
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bb->predecessors_count = 0;
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2022-06-20 15:34:44 +02:00
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ir_worklist_push(&worklist, b);
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} else {
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2022-11-10 22:19:17 +01:00
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bb->flags = IR_BB_UNREACHABLE; /* all blocks are marked as UNREACHABLE first */
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if (insn->op == IR_MERGE || insn->op == IR_LOOP_BEGIN) {
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n = ir_variable_inputs_count(insn);
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bb->predecessors_count = n;
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edges_count += n;
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count += n;
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2022-11-29 18:02:07 +01:00
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} else if (EXPECTED(insn->op1)) {
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2022-11-10 22:19:17 +01:00
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bb->predecessors_count = 1;
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edges_count++;
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count++;
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2022-11-29 18:02:07 +01:00
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} else {
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bb->predecessors_count = 0;
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2022-04-05 23:19:23 +02:00
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}
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}
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2022-11-10 22:19:17 +01:00
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b++;
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bb++;
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} IR_BITSET_FOREACH_END();
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2022-11-08 21:09:35 +01:00
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IR_ASSERT(count == edges_count * 2);
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2022-11-10 22:19:17 +01:00
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ir_mem_free(bb_starts);
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2022-04-05 23:19:23 +02:00
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2022-11-10 22:19:17 +01:00
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/* Create an array of successor/predecessors control edges */
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2022-04-05 23:19:23 +02:00
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edges = ir_mem_malloc(edges_count * 2 * sizeof(uint32_t));
|
|
|
|
bb = blocks + 1;
|
|
|
|
for (b = 1; b <= bb_count; b++, bb++) {
|
|
|
|
insn = &ctx->ir_base[bb->start];
|
2022-11-11 00:56:16 +01:00
|
|
|
if (bb->predecessors_count > 1) {
|
2022-11-10 22:19:17 +01:00
|
|
|
uint32_t *q = edges + bb->predecessors;
|
2022-11-09 19:56:31 +01:00
|
|
|
n = ir_variable_inputs_count(insn);
|
2022-11-10 22:19:17 +01:00
|
|
|
for (p = insn->ops + 1; n > 0; p++, q++, n--) {
|
2022-09-05 18:21:07 +02:00
|
|
|
ref = *p;
|
2022-11-09 19:56:31 +01:00
|
|
|
IR_ASSERT(ref);
|
|
|
|
ir_ref pred_b = _blocks[ref];
|
|
|
|
ir_block *pred_bb = &blocks[pred_b];
|
2022-11-10 22:19:17 +01:00
|
|
|
*q = pred_b;
|
|
|
|
edges[pred_bb->successors + pred_bb->successors_count++] = b;
|
2022-04-05 23:19:23 +02:00
|
|
|
}
|
2022-11-11 00:56:16 +01:00
|
|
|
} else if (bb->predecessors_count == 1) {
|
2022-09-05 18:21:07 +02:00
|
|
|
ref = insn->op1;
|
|
|
|
IR_ASSERT(ref);
|
|
|
|
IR_ASSERT(IR_OPND_KIND(ir_op_flags[insn->op], 1) == IR_OPND_CONTROL);
|
|
|
|
ir_ref pred_b = _blocks[ref];
|
|
|
|
ir_block *pred_bb = &blocks[pred_b];
|
2022-11-10 22:19:17 +01:00
|
|
|
edges[bb->predecessors] = pred_b;
|
|
|
|
edges[pred_bb->successors + pred_bb->successors_count++] = b;
|
2022-04-05 23:19:23 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-11-10 22:19:17 +01:00
|
|
|
ctx->cfg_blocks_count = bb_count;
|
|
|
|
ctx->cfg_edges_count = edges_count * 2;
|
|
|
|
ctx->cfg_blocks = blocks;
|
|
|
|
ctx->cfg_edges = edges;
|
|
|
|
ctx->cfg_map = _blocks;
|
2022-04-05 23:19:23 +02:00
|
|
|
|
2022-06-20 15:34:44 +02:00
|
|
|
/* Mark reachable blocks */
|
|
|
|
while (ir_worklist_len(&worklist) != 0) {
|
2022-11-10 22:19:17 +01:00
|
|
|
uint32_t *p;
|
2022-06-20 15:34:44 +02:00
|
|
|
|
|
|
|
b = ir_worklist_pop(&worklist);
|
|
|
|
bb = &blocks[b];
|
2022-11-10 22:19:17 +01:00
|
|
|
bb->flags &= ~IR_BB_UNREACHABLE;
|
2022-06-20 15:34:44 +02:00
|
|
|
n = bb->successors_count;
|
2022-11-10 22:19:17 +01:00
|
|
|
if (n > 1) {
|
|
|
|
for (p = edges + bb->successors; n > 0; p++, n--) {
|
|
|
|
ir_worklist_push(&worklist, *p);
|
2022-06-20 15:34:44 +02:00
|
|
|
}
|
2022-11-10 22:19:17 +01:00
|
|
|
} else if (n == 1) {
|
|
|
|
ir_worklist_push(&worklist, edges[bb->successors]);
|
2022-06-20 15:34:44 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
ir_worklist_free(&worklist);
|
|
|
|
|
2022-04-05 23:19:23 +02:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2022-11-29 18:02:07 +01:00
|
|
|
static void ir_remove_predecessor(ir_ctx *ctx, ir_block *bb, uint32_t from)
|
|
|
|
{
|
|
|
|
uint32_t i, *p, *q, n = 0;
|
|
|
|
|
|
|
|
p = q = &ctx->cfg_edges[bb->predecessors];
|
|
|
|
for (i = 0; i < bb->predecessors_count; i++, p++) {
|
|
|
|
if (*p != from) {
|
|
|
|
if (p != q) {
|
|
|
|
*q = *p;
|
|
|
|
}
|
|
|
|
q++;
|
|
|
|
n++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
IR_ASSERT(n != bb->predecessors_count);
|
|
|
|
bb->predecessors_count = n;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ir_remove_from_use_list(ir_ctx *ctx, ir_ref from, ir_ref ref)
|
|
|
|
{
|
|
|
|
ir_ref j, n, *p, *q, use;
|
|
|
|
ir_use_list *use_list = &ctx->use_lists[from];
|
|
|
|
ir_ref skip = 0;
|
|
|
|
|
|
|
|
n = use_list->count;
|
|
|
|
for (j = 0, p = q = &ctx->use_edges[use_list->refs]; j < n; j++, p++) {
|
|
|
|
use = *p;
|
|
|
|
if (use == ref) {
|
|
|
|
skip++;
|
|
|
|
} else {
|
|
|
|
if (p != q) {
|
|
|
|
*q = use;
|
|
|
|
}
|
|
|
|
q++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
use_list->count -= skip;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ir_remove_merge_input(ir_ctx *ctx, ir_ref merge, ir_ref from)
|
|
|
|
{
|
|
|
|
ir_ref i, j, n, k, *p, use;
|
|
|
|
ir_insn *use_insn;
|
|
|
|
ir_use_list *use_list;
|
|
|
|
ir_bitset life_inputs;
|
|
|
|
ir_insn *insn = &ctx->ir_base[merge];
|
|
|
|
|
|
|
|
IR_ASSERT(insn->op == IR_MERGE || insn->op == IR_LOOP_BEGIN);
|
|
|
|
n = insn->inputs_count;
|
|
|
|
if (n == 0) {
|
|
|
|
n = 3;
|
|
|
|
}
|
|
|
|
i = 1;
|
|
|
|
life_inputs = ir_bitset_malloc(n + 1);
|
|
|
|
for (j = 1; j <= n; j++) {
|
|
|
|
ir_ref input = ir_insn_op(insn, j);
|
|
|
|
|
|
|
|
if (input != from) {
|
|
|
|
if (i != j) {
|
|
|
|
ir_insn_set_op(insn, i, input);
|
|
|
|
}
|
|
|
|
ir_bitset_incl(life_inputs, j);
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
i--;
|
|
|
|
if (i == 1) {
|
|
|
|
insn->op = IR_BEGIN;
|
|
|
|
insn->inputs_count = 0;
|
|
|
|
use_list = &ctx->use_lists[merge];
|
|
|
|
for (k = 0, p = &ctx->use_edges[use_list->refs]; k < use_list->count; k++, p++) {
|
|
|
|
use = *p;
|
|
|
|
use_insn = &ctx->ir_base[use];
|
|
|
|
if (use_insn->op == IR_PHI) {
|
|
|
|
/* Convert PHI to COPY */
|
|
|
|
i = 2;
|
|
|
|
for (j = 2; j <= n; j++) {
|
|
|
|
ir_ref input = ir_insn_op(use_insn, j);
|
|
|
|
|
|
|
|
if (ir_bitset_in(life_inputs, j - 1)) {
|
|
|
|
use_insn->op1 = ir_insn_op(use_insn, j);
|
|
|
|
} else if (input > 0) {
|
|
|
|
ir_remove_from_use_list(ctx, input, use);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
use_insn->op = IR_COPY;
|
|
|
|
use_insn->op2 = IR_UNUSED;
|
|
|
|
use_insn->op3 = IR_UNUSED;
|
|
|
|
ir_remove_from_use_list(ctx, merge, use);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (i == 2) {
|
|
|
|
i = 0;
|
|
|
|
}
|
|
|
|
insn->inputs_count = i;
|
|
|
|
|
|
|
|
n++;
|
|
|
|
use_list = &ctx->use_lists[merge];
|
|
|
|
for (k = 0, p = &ctx->use_edges[use_list->refs]; k < use_list->count; k++, p++) {
|
|
|
|
use = *p;
|
|
|
|
use_insn = &ctx->ir_base[use];
|
|
|
|
if (use_insn->op == IR_PHI) {
|
|
|
|
i = 2;
|
|
|
|
for (j = 2; j <= n; j++) {
|
|
|
|
ir_ref input = ir_insn_op(use_insn, j);
|
|
|
|
|
|
|
|
if (ir_bitset_in(life_inputs, j - 1)) {
|
|
|
|
IR_ASSERT(input);
|
|
|
|
if (i != j) {
|
|
|
|
ir_insn_set_op(use_insn, i, input);
|
|
|
|
}
|
|
|
|
i++;
|
|
|
|
} else if (input > 0) {
|
|
|
|
ir_remove_from_use_list(ctx, input, use);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
ir_mem_free(life_inputs);
|
|
|
|
ir_remove_from_use_list(ctx, from, merge);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* CFG constructed after SCCP pass doesn't have unreachable BBs, otherwise they should be removed */
|
|
|
|
int ir_remove_unreachable_blocks(ir_ctx *ctx)
|
|
|
|
{
|
|
|
|
uint32_t b, *p, i;
|
|
|
|
uint32_t unreachable_count = 0;
|
|
|
|
uint32_t bb_count = ctx->cfg_blocks_count;
|
|
|
|
ir_block *bb = ctx->cfg_blocks + 1;
|
|
|
|
|
|
|
|
for (b = 1; b <= bb_count; b++, bb++) {
|
|
|
|
if (bb->flags & IR_BB_UNREACHABLE) {
|
|
|
|
#if 0
|
|
|
|
do {if (!unreachable_count) ir_dump_cfg(ctx, stderr);} while(0);
|
|
|
|
#endif
|
|
|
|
if (bb->successors_count) {
|
|
|
|
for (i = 0, p = &ctx->cfg_edges[bb->successors]; i < bb->successors_count; i++, p++) {
|
|
|
|
ir_block *succ_bb = &ctx->cfg_blocks[*p];
|
|
|
|
|
|
|
|
if (!(succ_bb->flags & IR_BB_UNREACHABLE)) {
|
|
|
|
ir_remove_predecessor(ctx, succ_bb, b);
|
|
|
|
ir_remove_merge_input(ctx, succ_bb->start, bb->end);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ir_ref prev, ref = bb->end;
|
|
|
|
ir_insn *insn = &ctx->ir_base[ref];
|
|
|
|
|
|
|
|
IR_ASSERT(ir_op_flags[insn->op] & IR_OP_FLAG_TERMINATOR);
|
|
|
|
/* remove from terminators list */
|
|
|
|
prev = ctx->ir_base[1].op1;
|
|
|
|
if (prev == ref) {
|
|
|
|
ctx->ir_base[1].op1 = insn->op3;
|
|
|
|
} else {
|
|
|
|
while (prev) {
|
|
|
|
if (ctx->ir_base[prev].op3 == ref) {
|
|
|
|
ctx->ir_base[prev].op3 = insn->op3;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
prev = ctx->ir_base[prev].op3;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
ctx->cfg_map[bb->start] = 0;
|
|
|
|
ctx->cfg_map[bb->end] = 0;
|
|
|
|
unreachable_count++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (unreachable_count) {
|
|
|
|
ir_block *dst_bb;
|
|
|
|
uint32_t n = 1;
|
|
|
|
uint32_t *edges;
|
|
|
|
|
|
|
|
dst_bb = bb = ctx->cfg_blocks + 1;
|
|
|
|
for (b = 1; b <= bb_count; b++, bb++) {
|
|
|
|
if (!(bb->flags & IR_BB_UNREACHABLE)) {
|
|
|
|
if (dst_bb != bb) {
|
|
|
|
memcpy(dst_bb, bb, sizeof(ir_block));
|
|
|
|
ctx->cfg_map[dst_bb->start] = n;
|
|
|
|
ctx->cfg_map[dst_bb->end] = n;
|
|
|
|
}
|
|
|
|
dst_bb->successors_count = 0;
|
|
|
|
dst_bb++;
|
|
|
|
n++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
ctx->cfg_blocks_count = bb_count = n - 1;
|
|
|
|
|
|
|
|
/* Rebuild successor/predecessors control edges */
|
|
|
|
edges = ctx->cfg_edges;
|
|
|
|
bb = ctx->cfg_blocks + 1;
|
|
|
|
for (b = 1; b <= bb_count; b++, bb++) {
|
|
|
|
ir_insn *insn = &ctx->ir_base[bb->start];
|
|
|
|
ir_ref *p, ref;
|
|
|
|
|
|
|
|
if (bb->predecessors_count > 1) {
|
|
|
|
uint32_t *q = edges + bb->predecessors;
|
|
|
|
n = ir_variable_inputs_count(insn);
|
|
|
|
for (p = insn->ops + 1; n > 0; p++, q++, n--) {
|
|
|
|
ref = *p;
|
|
|
|
IR_ASSERT(ref);
|
|
|
|
ir_ref pred_b = ctx->cfg_map[ref];
|
|
|
|
ir_block *pred_bb = &ctx->cfg_blocks[pred_b];
|
|
|
|
*q = pred_b;
|
|
|
|
edges[pred_bb->successors + pred_bb->successors_count++] = b;
|
|
|
|
}
|
|
|
|
} else if (bb->predecessors_count == 1) {
|
|
|
|
ref = insn->op1;
|
|
|
|
IR_ASSERT(ref);
|
|
|
|
IR_ASSERT(IR_OPND_KIND(ir_op_flags[insn->op], 1) == IR_OPND_CONTROL);
|
|
|
|
ir_ref pred_b = ctx->cfg_map[ref];
|
|
|
|
ir_block *pred_bb = &ctx->cfg_blocks[pred_b];
|
|
|
|
edges[bb->predecessors] = pred_b;
|
|
|
|
edges[pred_bb->successors + pred_bb->successors_count++] = b;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2022-04-05 23:19:23 +02:00
|
|
|
static void compute_postnum(const ir_ctx *ctx, uint32_t *cur, uint32_t b)
|
|
|
|
{
|
|
|
|
uint32_t i, *p;
|
|
|
|
ir_block *bb = &ctx->cfg_blocks[b];
|
|
|
|
|
|
|
|
if (bb->postnum != 0) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (bb->successors_count) {
|
|
|
|
bb->postnum = -1; /* Marker for "currently visiting" */
|
|
|
|
p = ctx->cfg_edges + bb->successors;
|
|
|
|
i = bb->successors_count;
|
|
|
|
do {
|
|
|
|
compute_postnum(ctx, cur, *p);
|
|
|
|
p++;
|
|
|
|
} while (--i);
|
|
|
|
}
|
|
|
|
bb->postnum = (*cur)++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Computes dominator tree using algorithm from "A Simple, Fast Dominance Algorithm" by
|
|
|
|
* Cooper, Harvey and Kennedy. */
|
|
|
|
int ir_build_dominators_tree(ir_ctx *ctx)
|
|
|
|
{
|
2022-09-14 22:59:54 +02:00
|
|
|
uint32_t blocks_count, b, postnum;
|
2022-04-05 23:19:23 +02:00
|
|
|
ir_block *blocks, *bb;
|
|
|
|
uint32_t *edges;
|
|
|
|
bool changed;
|
|
|
|
|
2022-09-14 22:59:54 +02:00
|
|
|
postnum = 1;
|
|
|
|
compute_postnum(ctx, &postnum, 1);
|
|
|
|
|
|
|
|
if (ctx->ir_base[1].op2) {
|
|
|
|
for (b = 2, bb = &ctx->cfg_blocks[2]; b <= ctx->cfg_blocks_count; b++, bb++) {
|
|
|
|
if (bb->flags & IR_BB_ENTRY) {
|
|
|
|
compute_postnum(ctx, &postnum, b);
|
|
|
|
bb->idom = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
ctx->cfg_blocks[1].postnum = postnum;
|
|
|
|
}
|
2022-04-05 23:19:23 +02:00
|
|
|
|
|
|
|
/* Find immediate dominators */
|
|
|
|
blocks = ctx->cfg_blocks;
|
|
|
|
edges = ctx->cfg_edges;
|
|
|
|
blocks_count = ctx->cfg_blocks_count;
|
|
|
|
blocks[1].idom = 1;
|
|
|
|
do {
|
|
|
|
changed = 0;
|
|
|
|
/* Iterating in Reverse Post Oorder */
|
|
|
|
for (b = 2, bb = &blocks[2]; b <= blocks_count; b++, bb++) {
|
2022-11-29 18:02:07 +01:00
|
|
|
IR_ASSERT(!(bb->flags & IR_BB_UNREACHABLE));
|
2022-09-14 22:59:54 +02:00
|
|
|
if (bb->predecessors_count == 1) {
|
2022-11-08 21:09:35 +01:00
|
|
|
uint32_t idom = 0;
|
2022-09-14 22:59:54 +02:00
|
|
|
uint32_t pred_b = edges[bb->predecessors];
|
|
|
|
ir_block *pred_bb = &blocks[pred_b];
|
|
|
|
|
|
|
|
if (pred_bb->idom > 0) {
|
|
|
|
idom = pred_b;
|
|
|
|
}
|
|
|
|
if (idom > 0 && bb->idom != idom) {
|
|
|
|
bb->idom = idom;
|
|
|
|
changed = 1;
|
|
|
|
}
|
|
|
|
} else if (bb->predecessors_count) {
|
2022-11-08 21:09:35 +01:00
|
|
|
uint32_t idom = 0;
|
2022-04-05 23:19:23 +02:00
|
|
|
uint32_t k = bb->predecessors_count;
|
|
|
|
uint32_t *p = edges + bb->predecessors;
|
|
|
|
do {
|
|
|
|
uint32_t pred_b = *p;
|
|
|
|
ir_block *pred_bb = &blocks[pred_b];
|
|
|
|
|
2022-09-14 22:59:54 +02:00
|
|
|
if (pred_bb->idom > 0 && !(pred_bb->flags & IR_BB_ENTRY)) {
|
2022-04-05 23:19:23 +02:00
|
|
|
if (idom == 0) {
|
|
|
|
idom = pred_b;
|
|
|
|
} else if (idom != pred_b) {
|
|
|
|
ir_block *idom_bb = &blocks[idom];
|
|
|
|
|
|
|
|
do {
|
|
|
|
while (pred_bb->postnum < idom_bb->postnum) {
|
|
|
|
pred_b = pred_bb->idom;
|
|
|
|
pred_bb = &blocks[pred_b];
|
|
|
|
}
|
|
|
|
while (idom_bb->postnum < pred_bb->postnum) {
|
|
|
|
idom = idom_bb->idom;
|
|
|
|
idom_bb = &blocks[idom];
|
|
|
|
}
|
|
|
|
} while (idom != pred_b);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
p++;
|
|
|
|
} while (--k > 0);
|
|
|
|
|
|
|
|
if (idom > 0 && bb->idom != idom) {
|
|
|
|
bb->idom = idom;
|
|
|
|
changed = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} while (changed);
|
|
|
|
blocks[1].idom = 0;
|
|
|
|
blocks[1].dom_depth = 0;
|
|
|
|
|
|
|
|
/* Construct dominators tree */
|
|
|
|
for (b = 2, bb = &blocks[2]; b <= blocks_count; b++, bb++) {
|
2022-11-29 18:02:07 +01:00
|
|
|
IR_ASSERT(!(bb->flags & IR_BB_UNREACHABLE));
|
2022-09-14 22:59:54 +02:00
|
|
|
if (bb->flags & IR_BB_ENTRY) {
|
|
|
|
bb->idom = 0;
|
|
|
|
bb->dom_depth = 0;
|
|
|
|
} else if (bb->idom > 0) {
|
2022-04-05 23:19:23 +02:00
|
|
|
ir_block *idom_bb = &blocks[bb->idom];
|
|
|
|
|
|
|
|
bb->dom_depth = idom_bb->dom_depth + 1;
|
|
|
|
/* Sort by block number to traverse children in pre-order */
|
|
|
|
if (idom_bb->dom_child == 0) {
|
|
|
|
idom_bb->dom_child = b;
|
|
|
|
} else if (b < idom_bb->dom_child) {
|
|
|
|
bb->dom_next_child = idom_bb->dom_child;
|
|
|
|
idom_bb->dom_child = b;
|
|
|
|
} else {
|
|
|
|
int child = idom_bb->dom_child;
|
|
|
|
ir_block *child_bb = &blocks[child];
|
|
|
|
|
|
|
|
while (child_bb->dom_next_child > 0 && b > child_bb->dom_next_child) {
|
|
|
|
child = child_bb->dom_next_child;
|
|
|
|
child_bb = &blocks[child];
|
|
|
|
}
|
|
|
|
bb->dom_next_child = child_bb->dom_next_child;
|
|
|
|
child_bb->dom_next_child = b;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool ir_dominates(ir_block *blocks, uint32_t b1, uint32_t b2)
|
|
|
|
{
|
|
|
|
uint32_t b1_depth = blocks[b1].dom_depth;
|
|
|
|
ir_block *bb2 = &blocks[b2];
|
|
|
|
|
|
|
|
while (bb2->dom_depth > b1_depth) {
|
|
|
|
b2 = bb2->dom_parent;
|
|
|
|
bb2 = &blocks[b2];
|
|
|
|
}
|
|
|
|
return b1 == b2;
|
|
|
|
}
|
|
|
|
|
|
|
|
int ir_find_loops(ir_ctx *ctx)
|
|
|
|
{
|
|
|
|
uint32_t i, j, n, count;
|
|
|
|
uint32_t *entry_times, *exit_times, *sorted_blocks, time = 1;
|
|
|
|
ir_block *blocks = ctx->cfg_blocks;
|
|
|
|
uint32_t *edges = ctx->cfg_edges;
|
|
|
|
ir_worklist work;
|
|
|
|
|
|
|
|
/* We don't materialize the DJ spanning tree explicitly, as we are only interested in ancestor
|
|
|
|
* queries. These are implemented by checking entry/exit times of the DFS search. */
|
|
|
|
ir_worklist_init(&work, ctx->cfg_blocks_count + 1);
|
2022-09-15 10:57:01 +02:00
|
|
|
entry_times = ir_mem_malloc((ctx->cfg_blocks_count + 1) * 3 * sizeof(uint32_t));
|
2022-04-05 23:19:23 +02:00
|
|
|
exit_times = entry_times + ctx->cfg_blocks_count + 1;
|
|
|
|
sorted_blocks = exit_times + ctx->cfg_blocks_count + 1;
|
|
|
|
|
2022-09-15 10:57:01 +02:00
|
|
|
memset(entry_times, 0, (ctx->cfg_blocks_count + 1) * sizeof(uint32_t));
|
|
|
|
|
2022-04-05 23:19:23 +02:00
|
|
|
ir_worklist_push(&work, 1);
|
|
|
|
while (ir_worklist_len(&work)) {
|
|
|
|
ir_block *bb;
|
|
|
|
int child;
|
|
|
|
|
|
|
|
next:
|
|
|
|
i = ir_worklist_peek(&work);
|
|
|
|
if (!entry_times[i]) {
|
|
|
|
entry_times[i] = time++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Visit blocks immediately dominated by i. */
|
|
|
|
bb = &blocks[i];
|
|
|
|
for (child = bb->dom_child; child > 0; child = blocks[child].dom_next_child) {
|
|
|
|
if (ir_worklist_push(&work, child)) {
|
|
|
|
goto next;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Visit join edges. */
|
|
|
|
if (bb->successors_count) {
|
|
|
|
uint32_t *p = edges + bb->successors;
|
|
|
|
for (j = 0; j < bb->successors_count; j++,p++) {
|
|
|
|
uint32_t succ = *p;
|
|
|
|
|
|
|
|
if (blocks[succ].idom == i) {
|
|
|
|
continue;
|
|
|
|
} else if (ir_worklist_push(&work, succ)) {
|
|
|
|
goto next;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
exit_times[i] = time++;
|
|
|
|
ir_worklist_pop(&work);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Sort blocks by level, which is the opposite order in which we want to process them */
|
|
|
|
sorted_blocks[1] = 1;
|
|
|
|
j = 1;
|
|
|
|
n = 2;
|
|
|
|
while (j != n) {
|
|
|
|
i = j;
|
|
|
|
j = n;
|
|
|
|
for (; i < j; i++) {
|
|
|
|
int child;
|
|
|
|
for (child = blocks[sorted_blocks[i]].dom_child; child > 0; child = blocks[child].dom_next_child) {
|
|
|
|
sorted_blocks[n++] = child;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
count = n;
|
|
|
|
|
|
|
|
/* Identify loops. See Sreedhar et al, "Identifying Loops Using DJ Graphs". */
|
|
|
|
while (n > 1) {
|
|
|
|
i = sorted_blocks[--n];
|
|
|
|
ir_block *bb = &blocks[i];
|
|
|
|
|
|
|
|
if (bb->predecessors_count > 1) {
|
|
|
|
bool irreducible = 0;
|
|
|
|
uint32_t *p = &edges[bb->predecessors];
|
|
|
|
|
|
|
|
j = bb->predecessors_count;
|
|
|
|
do {
|
|
|
|
uint32_t pred = *p;
|
|
|
|
|
|
|
|
/* A join edge is one for which the predecessor does not
|
|
|
|
immediately dominate the successor. */
|
|
|
|
if (bb->idom != pred) {
|
|
|
|
/* In a loop back-edge (back-join edge), the successor dominates
|
|
|
|
the predecessor. */
|
|
|
|
if (ir_dominates(blocks, i, pred)) {
|
|
|
|
if (!ir_worklist_len(&work)) {
|
|
|
|
ir_bitset_clear(work.visited, ir_bitset_len(ir_worklist_capasity(&work)));
|
|
|
|
}
|
2023-03-14 17:54:46 +01:00
|
|
|
blocks[pred].loop_header = 0; /* support for merged loops */
|
2022-04-05 23:19:23 +02:00
|
|
|
ir_worklist_push(&work, pred);
|
|
|
|
} else {
|
|
|
|
/* Otherwise it's a cross-join edge. See if it's a branch
|
|
|
|
to an ancestor on the DJ spanning tree. */
|
2023-03-14 17:54:46 +01:00
|
|
|
if (entry_times[pred] > entry_times[i] && exit_times[pred] < exit_times[i]) {
|
|
|
|
irreducible = 1;
|
|
|
|
}
|
2022-04-05 23:19:23 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
p++;
|
|
|
|
} while (--j);
|
|
|
|
|
|
|
|
if (UNEXPECTED(irreducible)) {
|
|
|
|
// TODO: Support for irreducible loops ???
|
|
|
|
bb->flags |= IR_BB_IRREDUCIBLE_LOOP;
|
|
|
|
ctx->flags |= IR_IRREDUCIBLE_CFG;
|
|
|
|
while (ir_worklist_len(&work)) {
|
|
|
|
ir_worklist_pop(&work);
|
|
|
|
}
|
|
|
|
} else if (ir_worklist_len(&work)) {
|
|
|
|
bb->flags |= IR_BB_LOOP_HEADER;
|
|
|
|
while (ir_worklist_len(&work)) {
|
|
|
|
j = ir_worklist_pop(&work);
|
|
|
|
while (blocks[j].loop_header > 0) {
|
|
|
|
j = blocks[j].loop_header;
|
|
|
|
}
|
|
|
|
if (j != i) {
|
|
|
|
ir_block *bb = &blocks[j];
|
2022-11-08 21:09:35 +01:00
|
|
|
if (bb->idom == 0 && j != 1) {
|
2022-04-05 23:19:23 +02:00
|
|
|
/* Ignore blocks that are unreachable or only abnormally reachable. */
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
bb->loop_header = i;
|
|
|
|
if (bb->predecessors_count) {
|
|
|
|
uint32_t *p = &edges[bb->predecessors];
|
|
|
|
j = bb->predecessors_count;
|
|
|
|
do {
|
|
|
|
ir_worklist_push(&work, *p);
|
|
|
|
p++;
|
|
|
|
} while (--j);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (n = 1; n < count; n++) {
|
|
|
|
i = sorted_blocks[n];
|
|
|
|
ir_block *bb = &blocks[i];
|
|
|
|
if (bb->loop_header > 0) {
|
|
|
|
bb->loop_depth = blocks[bb->loop_header].loop_depth;
|
|
|
|
}
|
|
|
|
if (bb->flags & IR_BB_LOOP_HEADER) {
|
|
|
|
bb->loop_depth++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ir_mem_free(entry_times);
|
|
|
|
ir_worklist_free(&work);
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
2022-05-23 23:43:35 +02:00
|
|
|
|
2022-05-24 11:47:39 +02:00
|
|
|
/* A variation of "Top-down Positioning" algorithm described by
|
|
|
|
* Karl Pettis and Robert C. Hansen "Profile Guided Code Positioning"
|
2022-05-24 11:59:57 +02:00
|
|
|
*
|
|
|
|
* TODO: Switch to "Bottom-up Positioning" algorithm
|
2022-05-24 11:47:39 +02:00
|
|
|
*/
|
2022-05-23 23:43:35 +02:00
|
|
|
int ir_schedule_blocks(ir_ctx *ctx)
|
|
|
|
{
|
2022-08-12 18:25:10 +02:00
|
|
|
ir_bitqueue blocks;
|
2022-08-31 13:29:34 +02:00
|
|
|
uint32_t b, *p, successor, best_successor, j, last_non_empty = 0;
|
2022-05-23 23:43:35 +02:00
|
|
|
ir_block *bb, *successor_bb, *best_successor_bb;
|
2022-05-24 11:47:39 +02:00
|
|
|
ir_insn *insn;
|
2022-08-12 18:25:10 +02:00
|
|
|
uint32_t *list, *map;
|
2022-05-24 11:47:39 +02:00
|
|
|
uint32_t prob, best_successor_prob;
|
2022-05-23 23:43:35 +02:00
|
|
|
uint32_t count = 0;
|
|
|
|
bool reorder = 0;
|
|
|
|
|
2022-08-12 18:25:10 +02:00
|
|
|
ir_bitqueue_init(&blocks, ctx->cfg_blocks_count + 1);
|
|
|
|
blocks.pos = 0;
|
2022-05-23 23:43:35 +02:00
|
|
|
list = ir_mem_malloc(sizeof(uint32_t) * (ctx->cfg_blocks_count + 1) * 2);
|
|
|
|
map = list + (ctx->cfg_blocks_count + 1);
|
2022-08-31 13:29:34 +02:00
|
|
|
for (b = 1, bb = &ctx->cfg_blocks[1]; b <= ctx->cfg_blocks_count; b++, bb++) {
|
2022-11-18 11:59:49 +01:00
|
|
|
if (ctx->prev_ref[bb->end] == bb->start
|
2022-08-31 13:29:34 +02:00
|
|
|
&& bb->successors_count == 1
|
2023-01-24 09:48:21 +01:00
|
|
|
&& (ctx->ir_base[bb->end].op == IR_END || ctx->ir_base[bb->end].op == IR_LOOP_END)
|
2022-08-31 13:29:34 +02:00
|
|
|
&& !(bb->flags & IR_BB_DESSA_MOVES)) {
|
|
|
|
bb->flags |= IR_BB_EMPTY;
|
|
|
|
}
|
2022-08-12 18:25:10 +02:00
|
|
|
ir_bitset_incl(blocks.set, b);
|
2022-05-23 23:43:35 +02:00
|
|
|
}
|
|
|
|
|
2022-08-12 18:25:10 +02:00
|
|
|
while ((b = ir_bitqueue_pop(&blocks)) != (uint32_t)-1) {
|
2022-05-23 23:43:35 +02:00
|
|
|
bb = &ctx->cfg_blocks[b];
|
2022-08-31 13:29:34 +02:00
|
|
|
/* Start trace */
|
2022-05-23 23:43:35 +02:00
|
|
|
do {
|
2023-01-24 09:59:41 +01:00
|
|
|
if (bb->predecessors_count > 1
|
2023-02-14 12:07:54 +01:00
|
|
|
&& (ctx->flags & IR_MERGE_EMPTY_ENTRIES)) {
|
2022-08-31 13:29:34 +02:00
|
|
|
/* Insert empty ENTRY blocks */
|
|
|
|
for (j = 0, p = &ctx->cfg_edges[bb->predecessors]; j < bb->predecessors_count; j++, p++) {
|
2022-11-08 21:09:35 +01:00
|
|
|
uint32_t predecessor = *p;
|
2022-08-31 13:29:34 +02:00
|
|
|
|
|
|
|
if (ir_bitqueue_in(&blocks, predecessor)
|
|
|
|
&& (ctx->cfg_blocks[predecessor].flags & IR_BB_ENTRY)
|
|
|
|
&& ctx->cfg_blocks[predecessor].end == ctx->cfg_blocks[predecessor].start + 1) {
|
|
|
|
ir_bitqueue_del(&blocks, predecessor);
|
|
|
|
count++;
|
|
|
|
list[count] = predecessor;
|
|
|
|
map[predecessor] = count;
|
|
|
|
if (predecessor != count) {
|
|
|
|
reorder = 1;
|
|
|
|
}
|
|
|
|
if (!(bb->flags & IR_BB_EMPTY)) {
|
|
|
|
last_non_empty = b;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2022-05-23 23:43:35 +02:00
|
|
|
count++;
|
|
|
|
list[count] = b;
|
|
|
|
map[b] = count;
|
|
|
|
if (b != count) {
|
|
|
|
reorder = 1;
|
|
|
|
}
|
2022-08-31 13:29:34 +02:00
|
|
|
if (!(bb->flags & IR_BB_EMPTY)) {
|
|
|
|
last_non_empty = b;
|
2022-05-23 23:43:35 +02:00
|
|
|
}
|
|
|
|
best_successor_bb = NULL;
|
|
|
|
for (b = 0, p = &ctx->cfg_edges[bb->successors]; b < bb->successors_count; b++, p++) {
|
|
|
|
successor = *p;
|
2022-08-12 18:25:10 +02:00
|
|
|
if (ir_bitqueue_in(&blocks, successor)) {
|
2022-05-24 11:47:39 +02:00
|
|
|
successor_bb = &ctx->cfg_blocks[successor];
|
|
|
|
insn = &ctx->ir_base[successor_bb->start];
|
|
|
|
if (insn->op == IR_IF_TRUE || insn->op == IR_IF_FALSE || insn->op == IR_CASE_DEFAULT) {
|
|
|
|
prob = insn->op2;
|
|
|
|
} else if (insn->op == IR_CASE_VAL) {
|
|
|
|
prob = insn->op3;
|
|
|
|
} else {
|
|
|
|
prob = 0;
|
|
|
|
}
|
|
|
|
if (!best_successor_bb
|
|
|
|
|| successor_bb->loop_depth > best_successor_bb->loop_depth) {
|
2022-05-23 23:43:35 +02:00
|
|
|
// TODO: use block frequency
|
|
|
|
best_successor = successor;
|
|
|
|
best_successor_bb = successor_bb;
|
2022-05-24 11:47:39 +02:00
|
|
|
best_successor_prob = prob;
|
2022-08-31 13:29:34 +02:00
|
|
|
} else if ((best_successor_prob && prob
|
|
|
|
&& prob > best_successor_prob)
|
|
|
|
|| (!best_successor_prob && prob
|
|
|
|
&& prob > 100 / bb->successors_count)
|
|
|
|
|| (best_successor_prob && !prob
|
|
|
|
&& best_successor_prob < 100 / bb->successors_count)
|
|
|
|
|| (!best_successor_prob && !prob
|
|
|
|
&& (best_successor_bb->flags & IR_BB_EMPTY)
|
|
|
|
&& !(successor_bb->flags & IR_BB_EMPTY))) {
|
2022-05-24 11:47:39 +02:00
|
|
|
best_successor = successor;
|
|
|
|
best_successor_bb = successor_bb;
|
|
|
|
best_successor_prob = prob;
|
2022-05-23 23:43:35 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!best_successor_bb) {
|
2022-08-31 13:29:34 +02:00
|
|
|
/* Try to continue trace using the other successor of the last IF */
|
|
|
|
if ((bb->flags & IR_BB_EMPTY) && last_non_empty) {
|
|
|
|
bb = &ctx->cfg_blocks[last_non_empty];
|
|
|
|
if (bb->successors_count == 2) {
|
|
|
|
b = ctx->cfg_edges[bb->successors];
|
2022-05-23 23:43:35 +02:00
|
|
|
|
2022-08-12 18:25:10 +02:00
|
|
|
if (!ir_bitqueue_in(&blocks, b)) {
|
2022-08-31 13:29:34 +02:00
|
|
|
b = ctx->cfg_edges[bb->successors + 1];
|
2022-05-23 23:43:35 +02:00
|
|
|
}
|
2022-08-12 18:25:10 +02:00
|
|
|
if (ir_bitqueue_in(&blocks, b)) {
|
2022-05-23 23:43:35 +02:00
|
|
|
bb = &ctx->cfg_blocks[b];
|
2022-08-12 18:25:10 +02:00
|
|
|
ir_bitqueue_del(&blocks, b);
|
2022-05-23 23:43:35 +02:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2022-08-31 13:29:34 +02:00
|
|
|
/* End trace */
|
2022-05-23 23:43:35 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
b = best_successor;
|
|
|
|
bb = best_successor_bb;
|
2022-08-12 18:25:10 +02:00
|
|
|
ir_bitqueue_del(&blocks, b);
|
2022-05-23 23:43:35 +02:00
|
|
|
} while (1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reorder) {
|
2022-09-15 10:57:01 +02:00
|
|
|
ir_block *cfg_blocks = ir_mem_malloc(sizeof(ir_block) * (ctx->cfg_blocks_count + 1));
|
2022-05-23 23:43:35 +02:00
|
|
|
|
2022-09-15 10:57:01 +02:00
|
|
|
memset(ctx->cfg_blocks, 0, sizeof(ir_block));
|
2022-05-23 23:43:35 +02:00
|
|
|
for (b = 1, bb = cfg_blocks + 1; b <= count; b++, bb++) {
|
|
|
|
*bb = ctx->cfg_blocks[list[b]];
|
|
|
|
if (bb->dom_parent > 0) {
|
|
|
|
bb->dom_parent = map[bb->dom_parent];
|
|
|
|
}
|
|
|
|
if (bb->dom_child > 0) {
|
|
|
|
bb->dom_child = map[bb->dom_child];
|
|
|
|
}
|
|
|
|
if (bb->dom_next_child > 0) {
|
|
|
|
bb->dom_next_child = map[bb->dom_next_child];
|
|
|
|
}
|
|
|
|
if (bb->loop_header > 0) {
|
|
|
|
bb->loop_header = map[bb->loop_header];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
for (j = 0; j < ctx->cfg_edges_count; j++) {
|
|
|
|
if (ctx->cfg_edges[j] > 0) {
|
|
|
|
ctx->cfg_edges[j] = map[ctx->cfg_edges[j]];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
ir_mem_free(ctx->cfg_blocks);
|
|
|
|
ctx->cfg_blocks = cfg_blocks;
|
|
|
|
}
|
|
|
|
|
|
|
|
ir_mem_free(list);
|
2022-08-12 18:25:10 +02:00
|
|
|
ir_bitqueue_free(&blocks);
|
2022-05-23 23:43:35 +02:00
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
2022-06-06 21:36:11 +02:00
|
|
|
|
|
|
|
/* JMP target optimisation */
|
2022-11-08 21:09:35 +01:00
|
|
|
uint32_t ir_skip_empty_target_blocks(ir_ctx *ctx, uint32_t b)
|
2022-06-06 21:36:11 +02:00
|
|
|
{
|
2022-08-30 22:15:20 +02:00
|
|
|
ir_block *bb;
|
|
|
|
|
|
|
|
while (1) {
|
|
|
|
bb = &ctx->cfg_blocks[b];
|
|
|
|
|
2022-11-18 11:59:49 +01:00
|
|
|
if (ctx->prev_ref[bb->end] == bb->start
|
2022-08-30 22:15:20 +02:00
|
|
|
&& bb->successors_count == 1
|
2023-01-24 09:48:21 +01:00
|
|
|
&& (ctx->ir_base[bb->end].op == IR_END || ctx->ir_base[bb->end].op == IR_LOOP_END)
|
2022-08-30 22:15:20 +02:00
|
|
|
&& !(bb->flags & (IR_BB_START|IR_BB_ENTRY|IR_BB_DESSA_MOVES))) {
|
|
|
|
b = ctx->cfg_edges[bb->successors];
|
|
|
|
} else {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return b;
|
|
|
|
}
|
|
|
|
|
2022-11-08 21:09:35 +01:00
|
|
|
uint32_t ir_skip_empty_next_blocks(ir_ctx *ctx, uint32_t b)
|
2022-08-30 22:15:20 +02:00
|
|
|
{
|
|
|
|
ir_block *bb;
|
|
|
|
|
|
|
|
while (1) {
|
2022-08-30 23:01:15 +02:00
|
|
|
if (b > ctx->cfg_blocks_count) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-08-30 22:15:20 +02:00
|
|
|
bb = &ctx->cfg_blocks[b];
|
|
|
|
|
2022-11-18 11:59:49 +01:00
|
|
|
if (ctx->prev_ref[bb->end] == bb->start
|
2022-08-30 22:15:20 +02:00
|
|
|
&& bb->successors_count == 1
|
2023-01-24 09:48:21 +01:00
|
|
|
&& (ctx->ir_base[bb->end].op == IR_END || ctx->ir_base[bb->end].op == IR_LOOP_END)
|
2022-08-31 13:29:34 +02:00
|
|
|
&& !(bb->flags & (IR_BB_START|/*IR_BB_ENTRY|*/IR_BB_DESSA_MOVES))) {
|
2022-08-30 22:15:20 +02:00
|
|
|
b++;
|
|
|
|
} else {
|
|
|
|
break;
|
|
|
|
}
|
2022-06-06 21:36:11 +02:00
|
|
|
}
|
|
|
|
return b;
|
|
|
|
}
|
|
|
|
|
2022-11-08 21:09:35 +01:00
|
|
|
void ir_get_true_false_blocks(ir_ctx *ctx, uint32_t b, uint32_t *true_block, uint32_t *false_block, uint32_t *next_block)
|
2022-06-06 21:36:11 +02:00
|
|
|
{
|
|
|
|
ir_block *bb;
|
2022-09-02 10:00:40 +02:00
|
|
|
uint32_t *p, use_block;
|
2022-06-06 21:36:11 +02:00
|
|
|
|
|
|
|
*true_block = 0;
|
|
|
|
*false_block = 0;
|
|
|
|
bb = &ctx->cfg_blocks[b];
|
|
|
|
IR_ASSERT(ctx->ir_base[bb->end].op == IR_IF);
|
|
|
|
IR_ASSERT(bb->successors_count == 2);
|
|
|
|
p = &ctx->cfg_edges[bb->successors];
|
2022-09-02 10:00:40 +02:00
|
|
|
use_block = *p;
|
|
|
|
if (ctx->ir_base[ctx->cfg_blocks[use_block].start].op == IR_IF_TRUE) {
|
|
|
|
*true_block = ir_skip_empty_target_blocks(ctx, use_block);
|
|
|
|
use_block = *(p+1);
|
|
|
|
IR_ASSERT(ctx->ir_base[ctx->cfg_blocks[use_block].start].op == IR_IF_FALSE);
|
|
|
|
*false_block = ir_skip_empty_target_blocks(ctx, use_block);
|
|
|
|
} else {
|
|
|
|
IR_ASSERT(ctx->ir_base[ctx->cfg_blocks[use_block].start].op == IR_IF_FALSE);
|
|
|
|
*false_block = ir_skip_empty_target_blocks(ctx, use_block);
|
|
|
|
use_block = *(p+1);
|
|
|
|
IR_ASSERT(ctx->ir_base[ctx->cfg_blocks[use_block].start].op == IR_IF_TRUE);
|
|
|
|
*true_block = ir_skip_empty_target_blocks(ctx, use_block);
|
2022-06-06 21:36:11 +02:00
|
|
|
}
|
|
|
|
IR_ASSERT(*true_block && *false_block);
|
2022-08-30 22:15:20 +02:00
|
|
|
*next_block = b == ctx->cfg_blocks_count ? 0 : ir_skip_empty_next_blocks(ctx, b + 1);
|
2022-07-20 10:39:05 +02:00
|
|
|
}
|