ir/tests/x86/shl_001.irt

--TEST--
001: shl function
--TARGET--
x86
--ARGS--
-S
--CODE--
{
	l_1 = START(l_4);
	int32_t x = PARAM(l_1, "x", 1);
	int32_t y = PARAM(l_1, "y", 2);
	int32_t ret = SHL(x, y);
	l_4 = RETURN(l_1, ret);
}
--EXPECT--
test:
	movl 8(%esp), %ecx
	movl 4(%esp), %eax
	shll %cl, %eax
	retl
Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 09:56:22 +01:00			`--TEST--`
			`001: shl function`
			`--TARGET--`
			`x86`
			`--ARGS--`
			`-S`
			`--CODE--`
			`{`
			`l_1 = START(l_4);`
			`int32_t x = PARAM(l_1, "x", 1);`
			`int32_t y = PARAM(l_1, "y", 2);`
			`int32_t ret = SHL(x, y);`
			`l_4 = RETURN(l_1, ret);`
			`}`
			`--EXPECT--`
			`test:`
			`movl 8(%esp), %ecx`
More accurate spill loads optimization for instructions that reuse op1 register for result This also fixes possbile incorrect register-allocation/code-generation for SHIFT instuction on x86[_64] 2023-06-29 11:42:44 +02:00			`movl 4(%esp), %eax`
Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 09:56:22 +01:00			`shll %cl, %eax`
			`retl`