ir/tests/Windows-x86_64/mul_005.irt

--TEST--
005: mul function
--TARGET--
Windows-x86_64
--ARGS--
-S
--CODE--
{
	uint32_t c = 2;
	l_1 = START(l_4);
	uint16_t x = PARAM(l_1, "x", 1);
	uint16_t ret = MUL(c, x);
	l_4 = RETURN(l_1, ret);
}
--EXPECT--
test:
	movw %cx, %ax
	addw %ax, %ax
	retq
Add simple tests for Windows-x86_64 conv_004.irt and conv_010.irt fail with capstone 5 because of changes in movd/movq 2023-03-01 22:55:20 +01:00			`--TEST--`
			`005: mul function`
			`--TARGET--`
			`Windows-x86_64`
			`--ARGS--`
			`-S`
			`--CODE--`
			`{`
			`uint32_t c = 2;`
			`l_1 = START(l_4);`
			`uint16_t x = PARAM(l_1, "x", 1);`
			`uint16_t ret = MUL(c, x);`
			`l_4 = RETURN(l_1, ret);`
			`}`
			`--EXPECT--`
			`test:`
			`movw %cx, %ax`
More accurate spill loads optimization for instructions that reuse op1 register for result This also fixes possbile incorrect register-allocation/code-generation for SHIFT instuction on x86[_64] 2023-06-29 11:42:44 +02:00			`addw %ax, %ax`
Add simple tests for Windows-x86_64 conv_004.irt and conv_010.irt fail with capstone 5 because of changes in movd/movq 2023-03-01 22:55:20 +01:00			`retq`