ir/tests/x86_64/ra_014.irt

--TEST--
014: Register Allocation (SHL + SHL)
--TARGET--
x86_64
--ARGS--
-S
--CODE--
{
	l_1 = START(l_4);
	uint32_t x = PARAM(l_1, "x", 1);
	uint32_t y = PARAM(l_1, "y", 2);
	uint32_t ret = SHL(x, y);
	uint32_t ret2 = SHL(x, ret);
	l_4 = RETURN(l_1, ret2);
}
--EXPECT--
test:
	movl %esi, %ecx
	movl %edi, %eax
	shll %cl, %eax
	movl %eax, %ecx
	movl %edi, %eax
	shll %cl, %eax
	retq