ir/tests/x86_64/ra_015.irt

--TEST--
015: Register Allocation (SHL + SHL + reuse/vreg hint)
--TARGET--
x86_64
--ARGS--
-S
--CODE--
{
	l_1 = START(l_4);
	uint32_t x = PARAM(l_1, "x", 1);
	uint32_t y = PARAM(l_1, "y", 2);
	uint32_t ret = SHL(x, y);
	uint32_t ret2 = SHL(y, ret);
	l_4 = RETURN(l_1, ret2);
}
--EXPECT--
test:
	movl %esi, %ecx
	shll %cl, %edi
	movl %edi, %ecx
	movl %esi, %eax
	shll %cl, %eax
	retq
Add vreg hints 2022-04-15 15:02:23 +02:00			`--TEST--`
			`015: Register Allocation (SHL + SHL + reuse/vreg hint)`
Allow multi-target test suite 2022-05-25 16:38:22 +02:00			`--TARGET--`
			`x86_64`
Add vreg hints 2022-04-15 15:02:23 +02:00			`--ARGS--`
			`-S`
			`--CODE--`
			`{`
			`l_1 = START(l_4);`
			`uint32_t x = PARAM(l_1, "x", 1);`
			`uint32_t y = PARAM(l_1, "y", 2);`
			`uint32_t ret = SHL(x, y);`
			`uint32_t ret2 = SHL(y, ret);`
			`l_4 = RETURN(l_1, ret2);`
			`}`
			`--EXPECT--`
			`test:`
			`movl %esi, %ecx`
			`shll %cl, %edi`
			`movl %edi, %ecx`
Clenaup (remove unnecessary SHIFT case) 2022-05-16 13:36:27 +02:00			`movl %esi, %eax`
Add vreg hints 2022-04-15 15:02:23 +02:00			`shll %cl, %eax`
			`retq`