ir/tests/021.irt

--TEST--
021: Translation out of SSA (Figure 7 from "Translating Out of Static Single Assignment Form" by Sreedhar)
--ARGS--
--save --dump-live-ranges --dump-cfg
--CODE--
{
	uintptr_t c_1 = 0;
	bool c_2 = 0;
	bool c_3 = 1;
	int32_t c_4 = 1;
	l_1 = START(l_13);
	int32_t d_2 = PARAM(l_1, "x", 0);
	l_3 = END(l_1);
	l_4 = LOOP_BEGIN(l_3, l_9);
	int32_t d_5 = PHI(l_4, d_2, d_6);
	int32_t d_6 = ADD(d_5, c_4);
	l_7 = IF(l_4, d_6);
	l_8 = IF_TRUE(l_7);
	l_9 = LOOP_END(l_8, l_4);
	l_10 = IF_FALSE(l_7);
	l_11 = LOOP_EXIT(l_10, l_4);
	l_12 = BEGIN(l_11);
	l_13 = RETURN(l_12, d_5);
}
--EXPECT--
{
	uintptr_t c_1 = 0;
	bool c_2 = 0;
	bool c_3 = 1;
	int32_t c_4 = 1;
	l_1 = START(l_13);
	int32_t d_2 = PARAM(l_1, "x", 0);
	l_3 = END(l_1);
	l_4 = LOOP_BEGIN(l_3, l_9);
	int32_t d_5 = PHI(l_4, d_2, d_6);
	int32_t d_6 = ADD(d_5, c_4);
	l_7 = IF(l_4, d_6);
	l_8 = IF_TRUE(l_7);
	l_9 = LOOP_END(l_8, l_4);
	l_10 = IF_FALSE(l_7);
	l_11 = LOOP_EXIT(l_10, l_4);
	l_12 = BEGIN(l_11);
	l_13 = RETURN(l_12, d_5);
}
{ # CFG
BB1:
	start=1
	end=3
	successors(1) [BB2]
	dom_depth=0
	dom_children [BB2]
BB2:
	start=4
	end=7
	successors(2) [BB3, BB4]
	predecessors(2) [BB1, BB3]
	dom_parent=BB1
	dom_depth=1
	dom_children [BB3, BB4]
	LOOP_HEADER
	loop_depth=1
BB3:
	start=8
	end=9
	successors(1) [BB2]
	predecessors(1) [BB2]
	dom_parent=BB2
	dom_depth=2
	loop_header=BB2
	loop_depth=1
	mov R2 -> R1
BB4:
	start=10
	end=11
	successors(1) [BB5]
	predecessors(1) [BB2]
	dom_parent=BB2
	dom_depth=2
	dom_children [BB5]
BB5:
	start=12
	end=13
	predecessors(1) [BB4]
	dom_parent=BB4
	dom_depth=3
}
{ # LIVE-RANGES (vregs_count=2)
R1 (d_2, d_5): [2.2-8.0), [10.0-13.1), DEF(2.2), DEF(5.2), USE(6.1/1), USE(13.1/2)
R2 (d_6): [6.2-10.0), DEF(6.2), USE(7.1/2)
}