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Fixed code generation for imul

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This commit is contained in:
Dmitry Stogov 2023-12-14 14:19:27 +03:00
parent 1fa3f2b6ae
commit 16b8e1cf4b
1 changed files with 28 additions and 12 deletions
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40
ir_x86.dasc
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@ -3899,20 +3899,36 @@ static void ir_emit_mul_div_mod(ir_ctx *ctx, ir_ref def, ir_insn *insn)
ir_emit_load(ctx, type, op2_reg, op2); ir_emit_load(ctx, type, op2_reg, op2);
} }
if (insn->op == IR_MUL || insn->op == IR_MUL_OV) { if (insn->op == IR_MUL || insn->op == IR_MUL_OV) {
IR_ASSERT(!IR_IS_TYPE_SIGNED(insn->type)); if (IR_IS_TYPE_SIGNED(insn->type)) {
if (op2_reg != IR_REG_NONE) { if (op2_reg != IR_REG_NONE) {
if (IR_REG_SPILLED(op2_reg)) { if (IR_REG_SPILLED(op2_reg)) {
op2_reg = IR_REG_NUM(op2_reg); op2_reg = IR_REG_NUM(op2_reg);
ir_emit_load(ctx, type, op2_reg, op2); ir_emit_load(ctx, type, op2_reg, op2);
} }
| ASM_REG_OP mul, type, op2_reg | ASM_REG_OP imul, type, op2_reg
} else {
if (ir_rule(ctx, op2) & IR_FUSED) {
offset = ir_fuse_load(ctx, op2, &op2_reg);
} else { } else {
offset = ir_ref_spill_slot(ctx, op2, &op2_reg); if (ir_rule(ctx, op2) & IR_FUSED) {
offset = ir_fuse_load(ctx, op2, &op2_reg);
} else {
offset = ir_ref_spill_slot(ctx, op2, &op2_reg);
}
| ASM_MEM_OP imul, type, [Ra(op2_reg)+offset]
}
} else {
if (op2_reg != IR_REG_NONE) {
if (IR_REG_SPILLED(op2_reg)) {
op2_reg = IR_REG_NUM(op2_reg);
ir_emit_load(ctx, type, op2_reg, op2);
}
| ASM_REG_OP mul, type, op2_reg
} else {
if (ir_rule(ctx, op2) & IR_FUSED) {
offset = ir_fuse_load(ctx, op2, &op2_reg);
} else {
offset = ir_ref_spill_slot(ctx, op2, &op2_reg);
}
| ASM_MEM_OP mul, type, [Ra(op2_reg)+offset]
} }
| ASM_MEM_OP mul, type, [Ra(op2_reg)+offset]
} }
} else { } else {
if (IR_IS_TYPE_SIGNED(type)) { if (IR_IS_TYPE_SIGNED(type)) {