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This commit is contained in:
Dmitry Stogov 2022-05-26 21:19:42 +03:00
parent 77f7d7e2af
commit 8683331d60
1 changed files with 3 additions and 5 deletions
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8
TODO
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@ -18,24 +18,22 @@
? instruction selection
- xor, btsl=INCL, btrl=EXCL, btl=IN, bsr
- MOVZX to avoid a SHIFT and AND instruction
- Use CMOVcc to remove branches
- BURS ???
? register allocation
- hints and low priority registers (prevent allocating registers that are used as hints
tests/x86/ra_015.irt, tests/x86/combo_004.irt tests/x86/min_005.ir, tests/x86/min_006.irt)
- spill slot coalescing
- optimal spill code placement through resolution
- splinting (spill only at cold path if possible)
- optimisation of spill code placement (BB local or through resolution)
- separate INT and FP allocation phases (for performance)
? code generation
- COND
? 32-bit x86 back-end
- ABS_INT incorrect register allocation (tests/x86/abs_001.irt)
- ABS_INT incorrect register allocation (tests/x86/abs_001.irt)
- TAILCALL with stack arguments (tests/x86/tailcall_001.itr)
- 32-bit x86 back-end 64-bit integers support
(add_009.irt, conv_001.irt, conv_002.irt, conv_004.irt, conv_007.irt, conv_010.irt, sub_009.irt)
(add_009.irt, conv_001.irt, conv_002.irt, conv_004.irt, conv_010.irt, sub_009.irt)
- binary code emission without DynAsm ???
- modules (functions, data objecs, import, export, prototypes, forward declarations, memory segments, ref data, expr data)