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First opernad of IMUL3 can not be constant
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parent
54597bc862
commit
b043955723
10
ir_x86.dasc
10
ir_x86.dasc
@ -603,6 +603,9 @@ binop:
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}
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}
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break;
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case IR_IMUL3:
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flags = IR_USE_MUST_BE_IN_REG | IR_OP1_SHOULD_BE_IN_REG;
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break;
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case IR_SKIP_SHIFT:
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flags = IR_OP2_MUST_BE_IN_REG;
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goto shift;
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@ -842,7 +845,6 @@ cmp_fp:
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case IR_GUARD_NOT:
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flags = IR_OP2_SHOULD_BE_IN_REG;
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break;
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case IR_IMUL3:
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case IR_IJMP:
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flags = IR_OP2_SHOULD_BE_IN_REG;
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break;
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@ -1153,7 +1155,8 @@ binop_fp:
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return IR_MUL_PWR2; // shl op1, IR_LOG2(op2_insn->val.u64)
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} else if (IR_IS_TYPE_SIGNED(insn->type)
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&& ir_type_size[insn->type] != 1
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&& IR_IS_SIGNED_32BIT(op2_insn->val.i64)) {
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&& IR_IS_SIGNED_32BIT(op2_insn->val.i64)
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&& !IR_IS_CONST_REF(insn->op1)) {
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ir_match_fuse_load(ctx, insn->op1, bb);
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return IR_IMUL3;
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}
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@ -1178,7 +1181,8 @@ binop_fp:
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if (IR_IS_TYPE_SIGNED(insn->type) && ir_type_size[insn->type] != 1) {
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if ((ctx->flags & IR_OPT_CODEGEN) && IR_IS_CONST_REF(insn->op2)) {
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op2_insn = &ctx->ir_base[insn->op2];
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if (IR_IS_SIGNED_32BIT(op2_insn->val.i64)) {
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if (IR_IS_SIGNED_32BIT(op2_insn->val.i64)
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&& !IR_IS_CONST_REF(insn->op1)) {
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ir_match_fuse_load(ctx, insn->op1, bb);
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return IR_IMUL3;
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}
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