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Fix register allocation for MUL_OV in a different way

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Dmitry Stogov 2023-01-26 13:20:08 +03:00
parent 4fb50d85aa
commit bbfcb3e8c8
1 changed files with 1 additions and 2 deletions
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3
ir_aarch64.dasc
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@ -325,7 +325,6 @@ int ir_get_target_constraints(ir_ctx *ctx, ir_ref ref, ir_target_constraints *co
}
break;
case IR_MUL_OV:
flags |= IR_DEF_CONFLICTS_WITH_INPUT_REGS;
constraints->tmp_regs[n] = IR_TMP_REG(2, insn->type, IR_LOAD_SUB_REF, IR_SAVE_SUB_REF);
n++;
break;
@ -1376,8 +1375,8 @@ static void ir_emit_binop_int(ir_ctx *ctx, ir_ref def, ir_insn *insn)
if (IR_IS_TYPE_SIGNED(type)) {
tmp_reg = ctx->regs[def][3];
IR_ASSERT(tmp_reg != IR_REG_NONE);
| mul Rx(def_reg), Rx(op1_reg), Rx(op2_reg)
| smulh Rx(tmp_reg), Rx(op1_reg), Rx(op2_reg)
| mul Rx(def_reg), Rx(op1_reg), Rx(op2_reg)
| cmp Rx(tmp_reg), Rx(def_reg), asr #63
} else {
tmp_reg = ctx->regs[def][3];