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353 Commits

Author SHA1 Message Date
Dmitry Stogov
87f2fc7f69 Fixed typo 2023-05-29 15:52:17 +03:00
Dmitry Stogov
20b9a7513c Fixed missing label 2023-05-26 09:08:57 +03:00
Dmitry Stogov
2a80257535 Support for more C escape sequences 2023-05-22 19:51:19 +03:00
Dmitry Stogov
d3640495a2 Ceanup ir_compute_live_ranges() implementation 2023-05-19 12:34:54 +03:00
Dmitry Stogov
5c2023fd7f Avoid live range constrction for VARs 2023-05-18 21:00:57 +03:00
Dmitry Stogov
477dbf7d76 Avoid live range constrction for RLOAD with fixed registers 2023-05-18 13:37:12 +03:00
Dmitry Stogov
c9fa8dfebd Fixed SSA deconstruction 
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
 2023-05-17 22:37:45 +03:00
Dmitry Stogov
842f97cbcb Removed wrong code selection rule 2023-05-11 12:47:49 +03:00
Dmitry Stogov
6f8aa7b540 Add code selection rule to fuse 
movq 0x60(%r14), %rax
    leaq -1(%rax), %rax
    movq %rax, 0x60(%r14)
    testq %rax, %rax
    jle jit$$trace_exit_1

into

    subq $1, 0x60(%r14)
    jle jit$$trace_exit_1"
 2023-05-10 18:22:03 +03:00
Dmitry Stogov
1bbee7b9da Get rid of ir_live_interval.top 2023-04-28 09:49:12 +03:00
Dmitry Stogov
60802d942f Fix previous commit. We still need a temporary register for indirect calls. 2023-04-26 14:10:58 +03:00
Dmitry Stogov
9eb366698d Avoid reservaton of temporary resiser for argument passing 
We may use any scratch register that is not used for parameters
 2023-04-26 12:16:05 +03:00
Dmitry Stogov
0de0c1d0fa Improve parallel copy algorithm to support move of single source into multiple destinations 2023-04-26 10:56:55 +03:00
Dmitry Stogov
1749168078 Add ir_insn_len() and ir_insn_inputs_to_len() private helpers 2023-04-21 13:40:55 +03:00
Dmitry Stogov
e01c43a967 Simplify access to nodes with variable inputs count 2023-04-21 12:40:17 +03:00
Dmitry Stogov
56b0dbccde Use ir_ctx.mflags for CPU specific code-generation options 
'mflags' and ir_cpuinfo() return value have the same meaning.
 2023-04-18 09:54:35 +03:00
Dmitry Stogov
e5c01495da Use arena to allocate live_intervals and nested data structures 2023-04-13 13:47:16 +03:00
Dmitry Stogov
04795b9f04 Fix compilation warnings 2023-04-12 10:48:30 +03:00
Dmitry Stogov
1e5e9e08ce Re-implement instruction fusion and live-range construction 2023-04-05 19:20:43 +03:00
Dmitry Stogov
b109e2f2cd Disable LOAD fusion if there is a STORE or CALL between LOAD and its use 2023-03-30 19:07:21 +03:00
Dmitry Stogov
d79bd88f6f Improve x86 code generation for passing address of label to stack 
-       leal .L1, %eax
-       movl %eax, (%esp)
+       movl $.L1, (%esp)
 2023-03-29 15:48:41 +03:00
Dmitry Stogov
1058cde808 Cleanup instruction selector 2023-03-29 01:21:54 +03:00
Dmitry Stogov
e4b618ad00 Fix fusion of IF(_, CMP(AND(_, _) 0)) 2023-03-28 19:03:06 +03:00
Dmitry Stogov
2cf5f1a7ff typo 2023-03-28 16:59:46 +03:00
Dmitry Stogov
f058ecfc93 Prefer IR_TARGET_* checks instead of system specific macros 2023-03-28 13:40:44 +03:00
Dmitry Stogov
ba0fa44447 Add "const" modifiers 2023-03-28 13:18:12 +03:00
Dmitry Stogov
46f07a8222 Remove unnecessary checks 2023-03-24 00:51:08 +03:00
Dmitry Stogov
72a5649236 Reorder conditions and avoid reloading 2023-03-23 23:44:59 +03:00
Dmitry Stogov
7e687262f7 Remove always true conditions 2023-03-23 22:16:05 +03:00
Dmitry Stogov
87dbdcea0d Add necessary compensation loads for bounded nodes when enter into function through OSR entry-point 2023-03-21 13:45:37 +03:00
Dmitry Stogov
f5b7065b10 Refactor the ENTRY nodes 
Now all ENTRY nodes have a "fake" input control edge.
Through this edge all of them are dominated by START node.
 2023-03-17 09:02:37 +03:00
Dmitry Stogov
6e1848cb40 Add support for Windows TLS 2023-03-07 13:02:44 +03:00
Dmitry Stogov
5e13d47e38 Fix EXITCALL code for WIN64 (support for home/shadow space) 2023-03-07 11:25:22 +03:00
Dmitry Stogov
24f58e7759 Comment assertion to allow PHP/JIT/Win64 work 
Win64 calling convention defines volatile FP registers.
PHP JIT for Win64 saves and restores only GP registers.
This potentionaly may cause register clobbering and unexpected behavior.
 2023-03-03 16:04:54 +03:00
Dmitry Stogov
1542048331 Fix TAILCALL on WIN64 2023-03-02 22:08:24 +03:00
Dmitry Stogov
09d5ecc607 Fix support for WIN64 calling convention 2023-03-02 17:56:15 +03:00
Dmitry Stogov
5a48805c81 Add support for Windows-64 ABI ("home space") 
Fix parameter passing code to perform sign or zero extension when pass a regiser or a constant

TODO: ARM code maight need similar changes
 2023-03-02 13:27:01 +03:00
Dmitry Stogov
e2810c070e Save and restore used non-volatile XMM registers in prologue and epilogue. 
We currently save only "single double" part of the registers using
"movsd" instruction. In general, we should save and restore the whole XMM
registers.
 2023-02-28 18:12:29 +03:00
Dmitry Stogov
eb771b1fef Fix incorrect shift operand 2023-02-28 02:22:09 +03:00
Dmitry Stogov
9b34731d16 Fix most MSVC compilation warnings 2023-02-28 02:11:09 +03:00
Dmitry Stogov
00d5e471ad Improve load fusion, register allocateion and code selection for ADD 2023-02-21 22:55:47 +03:00
Dmitry Stogov
637fe28e90 Add comments 2023-02-21 15:41:41 +03:00
Arnaud Le Blanc
e95cdd0722 Fix temporary register allocation for IR_STORE_INT 
ir_get_target_constraints() mistakenly tests the instruction type and value
instead of the operands'.
 2023-02-18 13:18:49 +01:00
Dmitry Stogov
2f2fed89bb Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32") 2023-02-17 18:11:13 +03:00
Dmitry Stogov
c71076d3f0 Allow reservation stack for passing arguments 2023-02-17 15:52:26 +03:00
Dmitry Stogov
fd653528e9 JMP optimization. Lift constant IJMP targets into jmp_table(s). 2023-02-16 22:41:55 +03:00
Dmitry Stogov
ec8489bf6f Fix spill load 2023-02-16 01:46:16 +03:00
Dmitry Stogov
c7e2cca534 Add hint to reuse register in ZEXT/SEXT 2023-02-15 18:33:02 +03:00
Dmitry Stogov
1d7ab16c2a Allow load fuson for CALL and TAILCALL with arguments 2023-02-14 14:51:12 +03:00
Dmitry Stogov
e19ecd94c3 Eliminate unnecessary "test" or comparison instruction for IF(CMP_OP(BIN_OP(_, _), 0)) 
TODO: this should be ported to ARM
 2023-02-14 11:25:16 +03:00