Dmitry Stogov
|
0dbb794399
|
CI tests for MACOS build (#46)
|
2023-08-30 15:24:12 +03:00 |
|
Dmitry Stogov
|
7058c41411
|
More accurate spill loads optimization for instructions that reuse op1 register for result
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
|
2023-06-29 12:42:44 +03:00 |
|
Dmitry Stogov
|
8a5a81c03e
|
Improve live interval splitting and eliminate more redundand spill loads
|
2023-06-27 11:29:26 +03:00 |
|
Dmitry Stogov
|
678a6af863
|
Eliminate duplicate spill loads at the same basic block
|
2023-06-22 14:41:01 +03:00 |
|
Dmitry Stogov
|
35f94d570f
|
Revert "Eliminate duplicate spill loads at the same basic block"
This reverts commit 5d05d78462 .
|
2023-06-22 01:58:26 +03:00 |
|
Dmitry Stogov
|
5d05d78462
|
Eliminate duplicate spill loads at the same basic block
|
2023-06-22 01:24:50 +03:00 |
|
Dmitry Stogov
|
c9fa8dfebd
|
Fixed SSA deconstruction
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
|
2023-05-17 22:37:45 +03:00 |
|
Dmitry Stogov
|
9eb366698d
|
Avoid reservaton of temporary resiser for argument passing
We may use any scratch register that is not used for parameters
|
2023-04-26 12:16:05 +03:00 |
|
Dmitry Stogov
|
1e5e9e08ce
|
Re-implement instruction fusion and live-range construction
|
2023-04-05 19:20:43 +03:00 |
|
Dmitry Stogov
|
ee827ee983
|
Don't create two DEF UsePos
|
2023-03-29 17:22:49 +03:00 |
|
Dmitry Stogov
|
24e8e216a1
|
Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
|
2023-03-23 00:47:27 +03:00 |
|
Dmitry Stogov
|
2e31446e37
|
Better 'jp' elimination for IR_CMP_AND_BRANCH_FP
|
2023-02-07 01:57:07 +03:00 |
|
Dmitry Stogov
|
37dececa71
|
Add more tests (8 tests ara failed on 32-bit x86)
|
2022-11-08 11:56:22 +03:00 |
|