Dmitry Stogov
e60bb978f4
Use _xlat[] slots for "used constants" markers
2023-07-07 13:57:01 +03:00
Dmitry Stogov
4bb03ab7e3
ws
2023-07-07 11:53:11 +03:00
Dmitry Stogov
5b90420b18
Improved unused constant elimination
2023-07-07 11:15:52 +03:00
Dmitry Stogov
496a98708e
Improved IR linearization
2023-07-07 02:11:03 +03:00
Dmitry Stogov
ef201cd349
Use xlat[] directly (instead of "scheduled" bitset).
2023-07-06 19:34:20 +03:00
Dmitry Stogov
78c377ed2d
Store negarive block number in schedule_early() and postive in
...
schedule_late(). This eliminates a need for "visited" bitset.
2023-07-06 19:30:56 +03:00
Dmitry Stogov
d41abefd58
Move processing of the last node of the block out of the loop
2023-07-06 14:10:50 +03:00
Dmitry Stogov
59dbef0cfb
typo
2023-07-06 12:59:33 +03:00
Dmitry Stogov
f6cf9140da
Update ir_insn.inputs_count and use it after ir_build_def_use_lists()
2023-07-06 01:15:08 +03:00
Dmitry Stogov
d7d7d5fc1b
Implemented a faster ir_build_def_use_lists() with higher temporary memory requirement
2023-07-05 16:44:09 +03:00
Dmitry Stogov
8c331e3264
typo
2023-07-04 18:22:15 +03:00
Dmitry Stogov
da9c406cf5
Always build ir_ctx.cfg_map during scheduling (it's used for spill code placement)
2023-07-04 16:37:21 +03:00
Dmitry Stogov
19e08d42e9
Cleanup
2023-07-04 15:19:35 +03:00
Dmitry Stogov
ea7b921f1b
Cleanup
2023-07-04 12:19:24 +03:00
Dmitry Stogov
c52fa3e6e0
Clenaup and new folding rules
2023-07-04 12:15:38 +03:00
Dmitry Stogov
444806bd72
Fix Makefile
2023-07-04 10:36:15 +03:00
Dmitry Stogov
cf28a299cd
Fix Makefile dependencies
2023-07-04 10:03:33 +03:00
Dmitry Stogov
72a8fcf0f5
typo
2023-07-04 09:23:08 +03:00
Dmitry Stogov
5eb09ce7a5
Add comments
2023-07-04 09:22:28 +03:00
Dmitry Stogov
51d1bbbe09
Merge pull request #45 from weltling/example_func_call
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examples: Add native function call example
2023-07-03 09:37:56 +03:00
Anatol Belski
c437cc6df6
examples: Add native function call example
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Signed-off-by: Anatol Belski <anbelski@linux.microsoft.com>
2023-07-02 18:41:43 +02:00
Dmitry Stogov
ce2d6ceba6
Fixed non-boolean constant GUARD condition checks
2023-06-29 23:49:20 +03:00
Dmitry Stogov
7058c41411
More accurate spill loads optimization for instructions that reuse op1 register for result
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This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
2023-06-29 12:42:44 +03:00
Dmitry Stogov
865daeb988
Duxed support for multi-word instructions
2023-06-29 00:29:18 +03:00
Dmitry Stogov
2bfe1626ad
Change ir_allocate_blocked_reg() according to description from "Optimized Interval Splitting in a Linear Scan Register Allocator"
2023-06-28 22:00:50 +03:00
Dmitry Stogov
b1e6ae66e3
More accurate reslution of a register allocation conflict
2023-06-28 16:17:21 +03:00
Dmitry Stogov
1b88d998c8
Fixed inactive interval splitting
2023-06-27 15:48:35 +03:00
Dmitry Stogov
b9fc218604
Remove first part of splitted inactive interval from the "inactive" list
2023-06-27 15:04:10 +03:00
Dmitry Stogov
141d46f5d8
Fixed tests
2023-06-27 11:34:13 +03:00
Dmitry Stogov
8a5a81c03e
Improve live interval splitting and eliminate more redundand spill loads
2023-06-27 11:29:26 +03:00
Dmitry Stogov
9cec28c188
Fixed compilation warnings
2023-06-22 14:50:14 +03:00
Dmitry Stogov
678a6af863
Eliminate duplicate spill loads at the same basic block
2023-06-22 14:41:01 +03:00
Dmitry Stogov
85beed7901
Fixed incorrect oredering of moves during de-SSA
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Temporary de-SSA registers may conflict with outpot registers, therefore these output resisters should be assigned last.
2023-06-22 12:07:19 +03:00
Dmitry Stogov
35f94d570f
Revert "Eliminate duplicate spill loads at the same basic block"
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This reverts commit 5d05d78462
2023-06-22 01:58:26 +03:00
Dmitry Stogov
5d05d78462
Eliminate duplicate spill loads at the same basic block
2023-06-22 01:24:50 +03:00
Dmitry Stogov
bfb527509d
Fixed incorrect operands order
2023-06-21 23:56:47 +03:00
Dmitry Stogov
99bcde9e1e
Cleanup spill related code
2023-06-21 23:20:58 +03:00
Dmitry Stogov
d67c212916
Separate codegen info output into ir_dump_codegen()
2023-06-21 22:36:36 +03:00
Dmitry Stogov
ebaefd376a
Fix stack frame and assign all spill slots before code genearatin
2023-06-21 19:04:22 +03:00
Dmitry Stogov
4124ef5150
Allow printing IR annotated with register-allocation, spill-code-placement, de-SSA and code-generation information
2023-06-21 13:28:15 +03:00
Dmitry Stogov
25656607ba
Variabls with a register constraint may be loaed/stored directly from/to a spill slot (without an additional register)
2023-06-21 01:14:31 +03:00
Dmitry Stogov
ffac404552
Fix impossible load fusion
2023-06-20 12:14:52 +03:00
Dmitry Stogov
009e9c4a53
Split assign_regs() loop into two versions (with and without spilling).
2023-06-20 08:34:54 +03:00
Dmitry Stogov
0928b975be
Fixed incorrect buffer access
2023-06-19 21:34:50 +03:00
Dmitry Stogov
fc5e1742c6
Merge pull request #44 from weltling/capstone_toolset2
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ci: windows: Switch to Server 2019 runner image
2023-06-19 14:40:22 +03:00
Anatol Belski
d28de0e46e
ci: windows: Switch to Server 2019 runner image
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There seems to be a weird issue with toolset and host OS version, that
makes x86 Windows builds of capstone misbehave. It is not quite clear,
what is the exact issue, but switching to another runner image that also
uses a bit older toolset seems to help.
Signed-off-by: Anatol Belski <anbelski@linux.microsoft.com>
2023-06-16 23:02:00 +02:00
Dmitry Stogov
b37d4e0443
Allow usage of CPU stack slots for deoptimization
2023-06-16 02:14:02 +03:00
Dmitry Stogov
6a98514bdc
Move stack size related metricks to ir_ctx
2023-06-15 19:28:54 +03:00
Dmitry Stogov
311267714e
Use macros insted of bit ops
2023-06-14 20:23:32 +03:00
Dmitry Stogov
defd58cec3
Store proper %sp register value
2023-06-13 18:22:21 +03:00
