Dmitry Stogov
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7058c41411
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More accurate spill loads optimization for instructions that reuse op1 register for result
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
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2023-06-29 12:42:44 +03:00 |
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Dmitry Stogov
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2bfe1626ad
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Change ir_allocate_blocked_reg() according to description from "Optimized Interval Splitting in a Linear Scan Register Allocator"
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2023-06-28 22:00:50 +03:00 |
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Dmitry Stogov
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678a6af863
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Eliminate duplicate spill loads at the same basic block
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2023-06-22 14:41:01 +03:00 |
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Dmitry Stogov
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35f94d570f
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Revert "Eliminate duplicate spill loads at the same basic block"
This reverts commit 5d05d78462.
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2023-06-22 01:58:26 +03:00 |
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Dmitry Stogov
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5d05d78462
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Eliminate duplicate spill loads at the same basic block
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2023-06-22 01:24:50 +03:00 |
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Dmitry Stogov
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ebaefd376a
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Fix stack frame and assign all spill slots before code genearatin
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2023-06-21 19:04:22 +03:00 |
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Dmitry Stogov
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b8be0b9dd9
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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Dmitry Stogov
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c9fa8dfebd
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Fixed SSA deconstruction
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
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2023-05-17 22:37:45 +03:00 |
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Dmitry Stogov
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1e5e9e08ce
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Re-implement instruction fusion and live-range construction
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2023-04-05 19:20:43 +03:00 |
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Dmitry Stogov
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ee827ee983
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Don't create two DEF UsePos
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2023-03-29 17:22:49 +03:00 |
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Dmitry Stogov
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24e8e216a1
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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Dmitry Stogov
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37dececa71
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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