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219 Commits

Author SHA1 Message Date
Dmitry Stogov
49316643e7 Initial support for modules (incomplete) 2023-10-20 17:44:45 +03:00
Dmitry Stogov
9c4cabd19d Fix inerval flags reseting after coalescing 2023-10-13 13:57:48 +03:00
Dmitry Stogov
e884c6b84c Reset interfal flags that become wrong after coalescing 2023-10-13 12:51:14 +03:00
Dmitry Stogov
daa31b3200 Properly remove interval from active list 2023-10-13 11:12:15 +03:00
Dmitry Stogov
1970a16496 Fixed crash on dead PHI 2023-10-12 14:54:23 +03:00
Javier Eguiluz
2f4f8504d4
Fix some typos (#51) 2023-10-03 08:34:02 +03:00
Dmitry Stogov
51a37f159b Initial implementation of LLVM export 2023-09-28 20:44:45 +03:00
Dmitry Stogov
d032f87b4d Reduce number of useless spill loads 2023-09-12 23:32:25 +03:00
Dmitry Stogov
915edb8a6c Force spill load for fused and spiled virtual registers 2023-09-04 19:32:27 +03:00
Dmitry Stogov
6ec7e6f49d Avoid saving unspecified registers in the fixed stack frame 2023-08-31 18:17:26 +03:00
Dmitry Stogov
a25f85e5dd Fix support for difference in qsort_r/s() on Windows, MAC and GNU 2023-08-30 02:35:06 +03:00
Dmitry Stogov
439f202aed Support for difference in qsort_r() on MAC and GNU 2023-08-30 00:52:24 +03:00
Dmitry Stogov
dd2ecad299 Allow reuse of spill slots for objecs of smaller size 2023-08-02 13:20:13 +03:00
Dmitry Stogov
1d49fe6cc4 Reduce cost of disabled IR_ASSERT() 2023-07-27 11:16:00 +03:00
Dmitry Stogov
f6cf9140da Update ir_insn.inputs_count and use it after ir_build_def_use_lists() 2023-07-06 01:15:08 +03:00
Dmitry Stogov
da9c406cf5 Always build ir_ctx.cfg_map during scheduling (it's used for spill code placement) 2023-07-04 16:37:21 +03:00
Dmitry Stogov
72a8fcf0f5 typo 2023-07-04 09:23:08 +03:00
Dmitry Stogov
5eb09ce7a5 Add comments 2023-07-04 09:22:28 +03:00
Dmitry Stogov
7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result 
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
 2023-06-29 12:42:44 +03:00
Dmitry Stogov
865daeb988 Duxed support for multi-word instructions 2023-06-29 00:29:18 +03:00
Dmitry Stogov
2bfe1626ad Change ir_allocate_blocked_reg() according to description from "Optimized Interval Splitting in a Linear Scan Register Allocator" 2023-06-28 22:00:50 +03:00
Dmitry Stogov
b1e6ae66e3 More accurate reslution of a register allocation conflict 2023-06-28 16:17:21 +03:00
Dmitry Stogov
1b88d998c8 Fixed inactive interval splitting 2023-06-27 15:48:35 +03:00
Dmitry Stogov
b9fc218604 Remove first part of splitted inactive interval from the "inactive" list 2023-06-27 15:04:10 +03:00
Dmitry Stogov
8a5a81c03e Improve live interval splitting and eliminate more redundand spill loads 2023-06-27 11:29:26 +03:00
Dmitry Stogov
678a6af863 Eliminate duplicate spill loads at the same basic block 2023-06-22 14:41:01 +03:00
Dmitry Stogov
35f94d570f Revert "Eliminate duplicate spill loads at the same basic block" 
This reverts commit 5d05d78462.
 2023-06-22 01:58:26 +03:00
Dmitry Stogov
5d05d78462 Eliminate duplicate spill loads at the same basic block 2023-06-22 01:24:50 +03:00
Dmitry Stogov
ebaefd376a Fix stack frame and assign all spill slots before code genearatin 2023-06-21 19:04:22 +03:00
Dmitry Stogov
009e9c4a53 Split assign_regs() loop into two versions (with and without spilling). 2023-06-20 08:34:54 +03:00
Dmitry Stogov
b37d4e0443 Allow usage of CPU stack slots for deoptimization 2023-06-16 02:14:02 +03:00
Dmitry Stogov
6a98514bdc Move stack size related metricks to ir_ctx 2023-06-15 19:28:54 +03:00
Dmitry Stogov
311267714e Use macros insted of bit ops 2023-06-14 20:23:32 +03:00
Dmitry Stogov
6a8830c1dc Better usage of the register hints 2023-06-09 16:26:15 +03:00
Dmitry Stogov
b8be0b9dd9 Avoid loading of stack parameter to register if this is not necessary 2023-06-09 00:35:15 +03:00
Dmitry Stogov
c599cfbdf3 Fixed spill slot allocation 2023-06-07 18:37:37 +03:00
Dmitry Stogov
186dc6b0a6 Fixed GH issue #33: IR program failed to compile with "-O0" "-S" options 2023-06-05 18:22:12 +03:00
Dmitry Stogov
3b0de17cdd Added missing fixed interval 2023-06-01 11:00:39 +03:00
Dmitry Stogov
6009e376b7 Speed-up liner scan 
- Don't add allocated interval into "active" list, if it doesn't overlap
  with next unhandled
- More efficient selection of registers available for the whole range
 2023-06-01 00:48:21 +03:00
Dmitry Stogov
d3640495a2 Ceanup ir_compute_live_ranges() implementation 2023-05-19 12:34:54 +03:00
Dmitry Stogov
5c2023fd7f Avoid live range constrction for VARs 2023-05-18 21:00:57 +03:00
Dmitry Stogov
ef31712f26 Remove usused IR_LIVE_INTERVAL_REG_LOAD flag 2023-05-18 14:17:54 +03:00
Dmitry Stogov
477dbf7d76 Avoid live range constrction for RLOAD with fixed registers 2023-05-18 13:37:12 +03:00
Dmitry Stogov
b6517f2028 Split IR_LIVE_INTERVAL_HAS_HINTS into IR_LIVE_INTERVAL_HAS_HINT_REGS and 
IR_LIVE_INTERVAL_HAS_HINT_REFS
 2023-05-18 10:48:31 +03:00
Dmitry Stogov
c9fa8dfebd Fixed SSA deconstruction 
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
 2023-05-17 22:37:45 +03:00
Dmitry Stogov
af7117a3b7 Use cfg_map if available 2023-05-17 11:14:34 +03:00
Dmitry Stogov
d859591943 Inline fast path 2023-05-05 18:37:14 +03:00
Dmitry Stogov
c3fca224ff Introduce IR_OP_FLAG_PINNED and IR_BB_HAS_PHI/PI/PARAM/VAR flags 2023-05-05 16:59:22 +03:00
Dmitry Stogov
1150c80ca2 Fixed support for OSR ENTRY 2023-05-05 12:59:33 +03:00
Dmitry Stogov
76f44fa126 Implemented path-exploration based live ranges construction 
The algorithm is based on "Computing Liveness Sets for SSA-Form Programs",
Florian Brandner, Benoit Boissinot, Alain Darte, Benoit Dupont de Dinechin,
Fabrice Rastello. TR Inria RR-7503, 2011

In comparison to the existing bitset based approach, the new algorithm
is more memory-space efficient and faster on big functions.
 2023-05-05 02:01:53 +03:00