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2 Commits

Author SHA1 Message Date
Dmitry Stogov
7058c41411 More accurate spill loads optimization for instructions that reuse op1 register for result 
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
 2023-06-29 12:42:44 +03:00
Dmitry Stogov
37dececa71 Add more tests (8 tests ara failed on 32-bit x86) 2022-11-08 11:56:22 +03:00