Dmitry Stogov
|
03bb1d1c4d
|
Flush CPU cache
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2022-06-07 11:53:27 +03:00 |
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Dmitry Stogov
|
fbedabc5d8
|
cleanup
|
2022-06-07 10:17:41 +03:00 |
|
Dmitry Stogov
|
1108acf9b8
|
cleanup
|
2022-06-06 23:12:45 +03:00 |
|
Dmitry Stogov
|
ad052c59ab
|
cleanup
|
2022-06-06 22:36:11 +03:00 |
|
Dmitry Stogov
|
17797a4a84
|
cleanup
|
2022-06-06 18:10:41 +03:00 |
|
Dmitry Stogov
|
f6b81b14e9
|
Aarch64 back-end
|
2022-06-06 15:27:25 +03:00 |
|
Dmitry Stogov
|
054a70012e
|
Aarch64 back-end (incomplete)
|
2022-06-03 12:47:02 +03:00 |
|
Dmitry Stogov
|
c28fe2734d
|
Validate operand types
|
2022-06-03 11:23:05 +03:00 |
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Dmitry Stogov
|
30e11861dd
|
Aarch64 back-end (incomplete)
|
2022-06-03 00:38:49 +03:00 |
|
Dmitry Stogov
|
fb998c9058
|
Aarch64 back-end (incomplete)
|
2022-06-02 18:34:47 +03:00 |
|
Dmitry Stogov
|
2af3f0569d
|
Merge last changes from LuaJIT repo
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2022-06-02 15:26:58 +03:00 |
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Dmitry Stogov
|
ab8019e0cd
|
Aarch64 back-end (incomplete)
|
2022-06-02 15:12:56 +03:00 |
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Dmitry Stogov
|
77e5e4a62c
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DynAsm/ARM64: Temporary fix for "LSL Rx(dst), Rd(src), #imm" encoding
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2022-06-02 13:40:50 +03:00 |
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Dmitry Stogov
|
bb842b489c
|
Aarch64 backend support & unification
|
2022-06-01 18:16:32 +03:00 |
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Dmitry Stogov
|
1be868c779
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Start Aarch64 back-end
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2022-06-01 00:51:02 +03:00 |
|
Dmitry Stogov
|
91bddc09ed
|
Cleanup & unification
|
2022-06-01 00:34:45 +03:00 |
|
Dmitry Stogov
|
00c300fc9f
|
Start Aarch64 back-end
|
2022-05-31 11:22:31 +03:00 |
|
Dmitry Stogov
|
a45d40277c
|
Replace xmm(dst-IR_REG_XMM0) by xmm(dst-IR_REG_FP_FIRST)
|
2022-05-31 10:44:10 +03:00 |
|
Dmitry Stogov
|
ad8248af31
|
Cleanup
|
2022-05-31 00:23:04 +03:00 |
|
Dmitry Stogov
|
41f3e43cf7
|
cleanup
|
2022-05-27 13:18:04 +03:00 |
|
Dmitry Stogov
|
3e1816a71f
|
Fix register allocation for ABS_INT
|
2022-05-27 00:11:31 +03:00 |
|
Dmitry Stogov
|
2840227291
|
Fixed assertion
|
2022-05-26 21:44:36 +03:00 |
|
Dmitry Stogov
|
8683331d60
|
Update tasks
|
2022-05-26 21:19:42 +03:00 |
|
Dmitry Stogov
|
77f7d7e2af
|
SWITCH elated fixes
|
2022-05-26 20:58:07 +03:00 |
|
Dmitry Stogov
|
4a39bda507
|
Fix double passing in 32-bit x86
|
2022-05-26 18:26:37 +03:00 |
|
Dmitry Stogov
|
4974c301bc
|
Fix code generation for preserved registers and dessa moves
|
2022-05-26 18:08:39 +03:00 |
|
Dmitry Stogov
|
f5bbdeea27
|
Fix buffer overflow
|
2022-05-26 17:19:43 +03:00 |
|
Dmitry Stogov
|
62d7fa7147
|
Fix string argument passing
|
2022-05-26 16:34:01 +03:00 |
|
Dmitry Stogov
|
0eef46493e
|
Improve code generation
|
2022-05-26 16:01:29 +03:00 |
|
Dmitry Stogov
|
8aac74dfb7
|
Improve code generation
|
2022-05-26 15:52:42 +03:00 |
|
Dmitry Stogov
|
2917dbbd59
|
Fix register clobbering
|
2022-05-26 15:26:04 +03:00 |
|
Dmitry Stogov
|
4862d69609
|
Improve code generation by load fusing
|
2022-05-26 14:43:19 +03:00 |
|
Dmitry Stogov
|
4598bd5b12
|
Better 32/64-bit assertions
|
2022-05-26 13:37:15 +03:00 |
|
Dmitry Stogov
|
e9fe55faa0
|
Fix param spill-slot assignment in 32-bit back-end
|
2022-05-26 13:09:20 +03:00 |
|
Dmitry Stogov
|
e28a3c801e
|
Fix retutn FP numbers for 32-bit x86 back-end
|
2022-05-26 11:58:51 +03:00 |
|
Dmitry Stogov
|
7e782a291a
|
Extend disassembler to support .rodata section and IP relative data labels
|
2022-05-26 01:17:02 +03:00 |
|
Dmitry Stogov
|
ead2b69fc6
|
x86_32 backend (incomplete)
|
2022-05-25 22:00:18 +03:00 |
|
Dmitry Stogov
|
19e93fd3f6
|
Allow multi-target test suite
|
2022-05-25 17:38:22 +03:00 |
|
Dmitry Stogov
|
235c1f2d65
|
Fix stack parameter loading for x86_32
|
2022-05-25 15:53:21 +03:00 |
|
Dmitry Stogov
|
341e3b8083
|
Initial support for x86_32 backend (incomplete)
|
2022-05-25 14:58:39 +03:00 |
|
Dmitry Stogov
|
4747a22474
|
Update tasks
|
2022-05-25 12:04:33 +03:00 |
|
Dmitry Stogov
|
ac65d71964
|
ws
|
2022-05-25 12:02:31 +03:00 |
|
Dmitry Stogov
|
9215162833
|
Ger rid of ir_ctx.bb_num and double neaning of ir_ctx.prev_insn_len
|
2022-05-25 11:58:35 +03:00 |
|
Dmitry Stogov
|
740cac8e2f
|
Move ir_ctx.unused_live_ranges to local variable
|
2022-05-25 10:57:21 +03:00 |
|
Dmitry Stogov
|
ab220de623
|
Fitsr and last instructions of BB and leading PARAM, PHI, PI, VAR instructions don't need to be scheduled.
|
2022-05-25 09:43:53 +03:00 |
|
Dmitry Stogov
|
463002107a
|
Rename "gcm_blocks" into "cfg_map"
|
2022-05-25 09:33:47 +03:00 |
|
Dmitry Stogov
|
87e9780a5b
|
Fixed handling of constant references
|
2022-05-25 09:30:26 +03:00 |
|
Dmitry Stogov
|
58b67fec18
|
Topological sort of nodes in each basic block
|
2022-05-24 18:04:38 +03:00 |
|
Dmitry Stogov
|
ddd5b739db
|
Update tasks
|
2022-05-24 12:59:57 +03:00 |
|
Dmitry Stogov
|
04667faf22
|
Reorder blocks according to branch probability
|
2022-05-24 12:47:39 +03:00 |
|