218 Commits

Author	SHA1	Message	Date
Dmitry Stogov	84b2bac02c	Add more tests	2022-04-22 00:11:34 +03:00
Dmitry Stogov	c36efda8a5	Improve register allocation for commutative instructions ... - swap operands f this make sense - fix coalescing bug	2022-04-21 16:38:18 +03:00
Dmitry Stogov	20c9f2e92a	Add comment	2022-04-20 19:30:28 +03:00
Dmitry Stogov	ffdb53821d	Refactor constraint model ... Each instruction consist from 4 sub positions LOAD, USE, DEF, SAVE. Hardware constraints are modeled conectiong live intervals and fixed intervals to different sub-positions.	2022-04-20 18:53:15 +03:00
Dmitry Stogov	6b60d8fba9	Code generation for VLOAD and VSTORE	2022-04-19 22:35:29 +03:00
Dmitry Stogov	879c4e75f5	Update vreg hints when compacting	2022-04-15 16:14:42 +03:00
Dmitry Stogov	0922b7cd7f	Add vreg hints	2022-04-15 16:02:23 +03:00
Dmitry Stogov	9f24f34aca	Cleanup	2022-04-15 14:46:03 +03:00
Dmitry Stogov	3cb707522f	Allocate scratch (caller-saved) registers first	2022-04-15 14:22:35 +03:00
Dmitry Stogov	2c2f2dabab	Better use placement	2022-04-15 00:35:02 +03:00
Dmitry Stogov	3f6a6aa3ea	Better CPU constraint model and initial support for live interval splitting (incomplete)	2022-04-14 22:40:13 +03:00
Dmitry Stogov	58c80c48e0	Create fixed interval for a temporary register used for DESSA moves	2022-04-12 16:09:53 +03:00
Dmitry Stogov	14f4fdf29d	Added few more basic x86_64 tests	2022-04-08 00:29:49 +03:00
Dmitry Stogov	e2601c8e06	Improve JIT support for IR_CALL	2022-04-07 23:41:38 +03:00
Dmitry Stogov	02863d7dc9	Initial JIT support for IR_CALL	2022-04-07 18:08:06 +03:00
Dmitry Stogov	23bd7fb272	Add hints and fixed intrvals for parameters	2022-04-07 14:18:59 +03:00
Dmitry Stogov	5b34386f62	Register Allocator suppor for fixed registers, use positions and register hints (incomplete).	2022-04-07 11:11:57 +03:00
Dmitry Stogov	2937993190	Initial import	2022-04-06 00:19:23 +03:00