Dmitry Stogov
5c2023fd7f
Avoid live range constrction for VARs
2023-05-18 21:00:57 +03:00
Dmitry Stogov
c9fa8dfebd
Fixed SSA deconstruction
...
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
2023-05-17 22:37:45 +03:00
Dmitry Stogov
e01c43a967
Simplify access to nodes with variable inputs count
2023-04-21 12:40:17 +03:00
Dmitry Stogov
1e5e9e08ce
Re-implement instruction fusion and live-range construction
2023-04-05 19:20:43 +03:00
Dmitry Stogov
1058cde808
Cleanup instruction selector
2023-03-29 01:21:54 +03:00
Dmitry Stogov
ba0fa44447
Add "const" modifiers
2023-03-28 13:18:12 +03:00
Dmitry Stogov
72a5649236
Reorder conditions and avoid reloading
2023-03-23 23:44:59 +03:00
Dmitry Stogov
b1f2167ea5
Calculate number of ENTRY blocks during CFG construction to avoid an eaxtra loop for ctx->entries[] gathering at ir_match()
2023-03-22 10:21:56 +03:00
Dmitry Stogov
87dbdcea0d
Add necessary compensation loads for bounded nodes when enter into function through OSR entry-point
2023-03-21 13:45:37 +03:00
Dmitry Stogov
f5b7065b10
Refactor the ENTRY nodes
...
Now all ENTRY nodes have a "fake" input control edge.
Through this edge all of them are dominated by START node.
2023-03-17 09:02:37 +03:00
Dmitry Stogov
09d5ecc607
Fix support for WIN64 calling convention
2023-03-02 17:56:15 +03:00
Dmitry Stogov
300665700f
Adopt IR test engine for Windows (this requires php and diff installed)
2023-03-01 20:31:14 +03:00
Dmitry Stogov
9b34731d16
Fix most MSVC compilation warnings
2023-02-28 02:11:09 +03:00
Anatol Belski
964f5a0191
build: MSVC compatibility
...
Signed-off-by: Anatol Belski <ab@php.net>
2023-02-25 00:04:57 +01:00
Dmitry Stogov
208e0040ae
Prefer 'ADD [addr], %r1' over 'mov [addr], %r1; lea [%r1, %r2], %r3'
2022-12-28 22:24:42 +03:00
Dmitry Stogov
6a4e239773
Create a sparate pass to remove unreachableble CFG blocks.
...
SCCP pass removes unreachable blocks before CFG construction.
In case of -O0 or -O1 pipeline (without SCCP) it's simpler and faster
to unlink unreachable CFG blocks once, then check for reachability
in almost any compilation pass.
-O2 pipeline (with SCCP) don't need this pass.
2022-11-29 20:02:07 +03:00
Dmitry Stogov
a137adfdf9
Separate ir_build_prev_refs(). It's necessary only for -O0 pipeline.
2022-11-24 12:55:16 +03:00
Dmitry Stogov
bdb8e6a1da
Set ir_ctx.prev_ref[] elements for inner BB traversing
2022-11-23 16:16:08 +03:00
Dmitry Stogov
ef6c59ad8f
Avoid instruction selection for the first instructionis of basic blocks
2022-11-18 15:07:19 +03:00
Dmitry Stogov
dde8309108
Use reference to previous instruction instead of its length
2022-11-18 13:59:49 +03:00
Dmitry Stogov
3e3746d5cb
Refactor API that expose target CPU register constraints for register allocator
2022-11-17 23:30:35 +03:00
Dmitry Stogov
3535fd2fc4
Fix compilation warnings and signed/unsigned mess
2022-11-08 23:09:35 +03:00
Dmitry Stogov
cc56f12f13
Add LICENSE and copyright notices
2022-11-08 11:32:46 +03:00
Dmitry Stogov
3af9e1a062
Move some common code into ir_emit.c
2022-10-26 22:52:19 +03:00
Dmitry Stogov
1b84570aa3
Intoduce ir_emit.c that shuould keep common part for different targets
2022-10-26 22:06:07 +03:00
