Dmitry Stogov
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d60d92516d
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Fixed tests
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2023-10-20 17:50:31 +03:00 |
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Dmitry Stogov
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211884cf29
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Introduce API to load modules
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2023-10-11 22:55:25 +03:00 |
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Dmitry Stogov
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09829a9e69
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Fixed x86_64 calling convention for vararg functions
%al is used as a hidden register to specify the number of passed vector registers
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2023-09-27 10:23:34 +03:00 |
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Dmitry Stogov
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0dbb794399
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CI tests for MACOS build (#46)
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2023-08-30 15:24:12 +03:00 |
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Dmitry Stogov
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7058c41411
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More accurate spill loads optimization for instructions that reuse op1 register for result
This also fixes possbile incorrect register-allocation/code-generation
for SHIFT instuction on x86[_64]
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2023-06-29 12:42:44 +03:00 |
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Dmitry Stogov
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2bfe1626ad
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Change ir_allocate_blocked_reg() according to description from "Optimized Interval Splitting in a Linear Scan Register Allocator"
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2023-06-28 22:00:50 +03:00 |
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Dmitry Stogov
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8a5a81c03e
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Improve live interval splitting and eliminate more redundand spill loads
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2023-06-27 11:29:26 +03:00 |
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Dmitry Stogov
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678a6af863
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Eliminate duplicate spill loads at the same basic block
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2023-06-22 14:41:01 +03:00 |
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Dmitry Stogov
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35f94d570f
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Revert "Eliminate duplicate spill loads at the same basic block"
This reverts commit 5d05d78462.
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2023-06-22 01:58:26 +03:00 |
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Dmitry Stogov
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5d05d78462
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Eliminate duplicate spill loads at the same basic block
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2023-06-22 01:24:50 +03:00 |
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Dmitry Stogov
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ebaefd376a
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Fix stack frame and assign all spill slots before code genearatin
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2023-06-21 19:04:22 +03:00 |
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Dmitry Stogov
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b8be0b9dd9
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Avoid loading of stack parameter to register if this is not necessary
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2023-06-09 00:35:15 +03:00 |
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Dmitry Stogov
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c9d3804b6e
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Fixed mistakes in GCM algorithm
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2023-05-29 17:02:50 +03:00 |
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Dmitry Stogov
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75edc8fec5
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Added type compatibility assertion and fixed mistakes in tests
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2023-05-22 20:48:07 +03:00 |
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Dmitry Stogov
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c9fa8dfebd
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Fixed SSA deconstruction
Previously we performed parallel copy for virtual registers, now we do
the same for the target CPU registers.
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2023-05-17 22:37:45 +03:00 |
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Dmitry Stogov
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60802d942f
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Fix previous commit. We still need a temporary register for indirect calls.
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2023-04-26 14:10:58 +03:00 |
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Dmitry Stogov
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9eb366698d
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Avoid reservaton of temporary resiser for argument passing
We may use any scratch register that is not used for parameters
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2023-04-26 12:16:05 +03:00 |
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Dmitry Stogov
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f85f5fd2a8
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Remove data dependency between TAILCALL and UNREACHABLE
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2023-04-13 02:41:28 +03:00 |
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Dmitry Stogov
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efa8a83153
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Fix spilling code for arguments passed theought stack and change RA to
prefer reusing the same register for splitted intervals
i# utils/
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2023-04-06 00:16:49 +03:00 |
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Dmitry Stogov
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1e5e9e08ce
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Re-implement instruction fusion and live-range construction
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2023-04-05 19:20:43 +03:00 |
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Dmitry Stogov
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ee827ee983
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Don't create two DEF UsePos
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2023-03-29 17:22:49 +03:00 |
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Dmitry Stogov
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d79bd88f6f
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Improve x86 code generation for passing address of label to stack
- leal .L1, %eax
- movl %eax, (%esp)
+ movl $.L1, (%esp)
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2023-03-29 15:48:41 +03:00 |
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Dmitry Stogov
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26e462fa42
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Add more folding rules
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2023-03-29 14:07:31 +03:00 |
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Dmitry Stogov
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24e8e216a1
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Remove a "reference" edge from LOOP_END to LOOP_BEGIN node.
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2023-03-23 00:47:27 +03:00 |
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Dmitry Stogov
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00d5e471ad
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Improve load fusion, register allocateion and code selection for ADD
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2023-02-21 22:55:47 +03:00 |
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Dmitry Stogov
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1d7ab16c2a
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Allow load fuson for CALL and TAILCALL with arguments
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2023-02-14 14:51:12 +03:00 |
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Dmitry Stogov
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2e31446e37
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Better 'jp' elimination for IR_CMP_AND_BRANCH_FP
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2023-02-07 01:57:07 +03:00 |
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Dmitry Stogov
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67da9e93ea
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Fix register clobbering during argument passing and spill load
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2022-12-26 20:25:11 +03:00 |
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Dmitry Stogov
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d26b162ffa
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Fix register clobbering during argument passing
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2022-12-26 18:27:53 +03:00 |
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Dmitry Stogov
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c6aeb417fa
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Extend test suite to support XFAIL section
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2022-11-22 10:43:29 +03:00 |
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Dmitry Stogov
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37dececa71
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Add more tests (8 tests ara failed on 32-bit x86)
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2022-11-08 11:56:22 +03:00 |
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