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Author SHA1 Message Date
Dmitry Stogov
29122c15c3 Add complex WIN64 tests 2023-03-02 17:57:26 +03:00
Dmitry Stogov
09d5ecc607 Fix support for WIN64 calling convention 2023-03-02 17:56:15 +03:00
Dmitry Stogov
c89a038fd3 Fix tests with capstone 5 
Different versions of capstone may disassemble MOVD/MOVQ differentrly
 2023-03-02 17:54:50 +03:00
Dmitry Stogov
5a48805c81 Add support for Windows-64 ABI ("home space") 
Fix parameter passing code to perform sign or zero extension when pass a regiser or a constant

TODO: ARM code maight need similar changes
 2023-03-02 13:27:01 +03:00
Dmitry Stogov
ebdeba9fff Add simple tests for Windows-x86_64 
conv_004.irt and conv_010.irt fail with capstone 5 because of changes in movd/movq
 2023-03-02 00:55:20 +03:00
Dmitry Stogov
49dd633620 Use separate target for Windows 64-bit 
Because of different ABI the generated asembler code differs from x86_64
 2023-03-02 00:52:51 +03:00
Dmitry Stogov
300665700f Adopt IR test engine for Windows (this requires php and diff installed) 2023-03-01 20:31:14 +03:00
Dmitry Stogov
e9a4b5efeb Fix MSVC compilation warnings 2023-03-01 14:18:06 +03:00
Dmitry Stogov
e2810c070e Save and restore used non-volatile XMM registers in prologue and epilogue. 
We currently save only "single double" part of the registers using
"movsd" instruction. In general, we should save and restore the whole XMM
registers.
 2023-02-28 18:12:29 +03:00
Dmitry Stogov
6b19fdb94f Fix WIN64 ABI (floating point non-volatiole registers) 2023-02-28 17:46:42 +03:00
Dmitry Stogov
c2e29a6dcc Emit error message in case of capstone failure 2023-02-28 15:36:08 +03:00
Dmitry Stogov
c658144736 Build ir_test.exe on Windows 2023-02-28 15:35:31 +03:00
Dmitry Stogov
9ded5ace4b Fix executable memory mapping for Windows 2023-02-28 15:34:36 +03:00
Dmitry Stogov
eb771b1fef Fix incorrect shift operand 2023-02-28 02:22:09 +03:00
Dmitry Stogov
9b34731d16 Fix most MSVC compilation warnings 2023-02-28 02:11:09 +03:00
Dmitry Stogov
81d87444af Use slash instead of backslash to prevent invalid escape sequences in #line directives generated by DynASM 2023-02-28 00:55:21 +03:00
Dmitry Stogov
6190cbb2e6
Merge pull request #8 from weltling/windows 
build: MSVC compatibility
 2023-02-28 00:01:40 +03:00
Anatol Belski
992d2d4f3a github: Set more descriptive job names 
Signed-off-by: Anatol Belski <ab@php.net>
 2023-02-25 00:04:58 +01:00
Anatol Belski
964f5a0191 build: MSVC compatibility 
Signed-off-by: Anatol Belski <ab@php.net>
 2023-02-25 00:04:57 +01:00
Anatol Belski
39c658b5d5 gitignore: Extend with some win32/ paths 
Signed-off-by: Anatol Belski <ab@php.net>
 2023-02-24 22:17:36 +01:00
Anatol Belski
ec11fc119b build: Add MSVC Makefile 
Signed-off-by: Anatol Belski <ab@php.net>
 2023-02-24 22:17:35 +01:00
Anatol Belski
e5c1a78746 ci: Extend with MSVC pass 
Signed-off-by: Anatol Belski <ab@php.net>
 2023-02-24 22:09:25 +01:00
Dmitry Stogov
c71bcb756a Fix macro 2023-02-24 17:06:19 +03:00
Dmitry Stogov
00d5e471ad Improve load fusion, register allocateion and code selection for ADD 2023-02-21 22:55:47 +03:00
Dmitry Stogov
8b4678a9ae Add "--dump-size" option 2023-02-21 22:22:41 +03:00
Dmitry Stogov
637fe28e90 Add comments 2023-02-21 15:41:41 +03:00
Dmitry Stogov
9f81982d86 Fix 'mov' to/from 'sp' register 
sp is shared with zero register and 'mov' for sp/xzr is encoded differently
 2023-02-21 11:42:05 +03:00
Dmitry Stogov
ab50cc3f05
Merge pull request #7 from arnaud-lb/fix-ir-store-int-tmp-reg 
Fix temporary register allocation for IR_STORE_INT
 2023-02-20 10:00:15 +03:00
Arnaud Le Blanc
e95cdd0722 Fix temporary register allocation for IR_STORE_INT 
ir_get_target_constraints() mistakenly tests the instruction type and value
instead of the operands'.
 2023-02-18 13:18:49 +01:00
Dmitry Stogov
2f2fed89bb Uze zero extended "mov" to load 64-bit register ("mov $u32, %r32") 2023-02-17 18:11:13 +03:00
Dmitry Stogov
c71076d3f0 Allow reservation stack for passing arguments 2023-02-17 15:52:26 +03:00
Dmitry Stogov
2bf6334f69 Remove "usafe" non-typed IR builder macros 
Usages of ctx->ir_base[] is not safe, because the array may be reallocated by any ir_emit/ir_fold call.
 2023-02-17 13:20:39 +03:00
Dmitry Stogov
28a5714a8e Use ANSI symbols 2023-02-17 09:11:38 +03:00
Dmitry Stogov
fd653528e9 JMP optimization. Lift constant IJMP targets into jmp_table(s). 2023-02-16 22:41:55 +03:00
Dmitry Stogov
31ea3153f3 Add (commeted) code that could eliminate register move for RSTORE 2023-02-16 17:49:30 +03:00
Dmitry Stogov
ec8489bf6f Fix spill load 2023-02-16 01:46:16 +03:00
Dmitry Stogov
c7e2cca534 Add hint to reuse register in ZEXT/SEXT 2023-02-15 18:33:02 +03:00
Dmitry Stogov
d07a2db592 Improve GCM to schedule floating nodes that depends only on constants 
(e.g. COPY(CONST)) to the last common ancestor.

Previously these nodes went to the first block.
 2023-02-15 15:18:42 +03:00
Dmitry Stogov
1d7ab16c2a Allow load fuson for CALL and TAILCALL with arguments 2023-02-14 14:51:12 +03:00
Dmitry Stogov
36553fdf14 Fix merging of empty ENTRY block with its successor 2023-02-14 14:07:54 +03:00
Dmitry Stogov
a02f39435a
Merge pull request #4 from weltling/makefile_simplify 
makefile: Simplify and regroup objects and targets
 2023-02-14 12:16:46 +03:00
Dmitry Stogov
320845fcf9 Update the picture 2023-02-14 11:52:50 +03:00
Dmitry Stogov
e19ecd94c3 Eliminate unnecessary "test" or comparison instruction for IF(CMP_OP(BIN_OP(_, _), 0)) 
TODO: this should be ported to ARM
 2023-02-14 11:25:16 +03:00
Anatol Belski
7b3dc08b05 makefile: Simplify and regroup objects and targets 
A small optimization to combine common pieces in the makefile.

- Use static pattern rules for the same operation
- Group headers prerequisities into own targets
- Reduce dups like objects to be listed just once in a var, etc.

Signed-off-by: Anatol Belski <ab@php.net>
 2023-02-14 00:23:45 +01:00
Dmitry Stogov
d19685375c Add few missing IR builder macros 2023-02-13 20:55:54 +03:00
Dmitry Stogov
a96defc13b Fix ir_TLS() macro 2023-02-13 20:26:36 +03:00
Dmitry Stogov
ab994122e7
Merge pull request #6 from nielsdos/fix-use-list 
Fix SCCP use list update for op3
 2023-02-13 09:37:52 +03:00
Dmitry Stogov
df8bf5cc5a
Merge pull request #5 from nielsdos/fix-i64-check 
Fix incorrect val.i64 check
 2023-02-13 09:32:07 +03:00
Niels Dossche
1e772c500e Fix SCCP use list update for op3 2023-02-12 14:18:17 +01:00
Niels Dossche
9d3354e89e Fix incorrect val.i64 check 2023-02-12 14:11:31 +01:00